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  • Tsai W, Lan Y, Hu Y and Chen S. (2012). Networks on chips: structure and design methodologies. Journal of Electrical and Computer Engineering. 2012. (2-2). Online publication date: 1-Jan-2012.

    https://doi.org/10.1155/2012/509465

  • Lan Y, Lo S, Lin Y, Hu Y and Chen S. BiNoC. Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip. (266-275).

    https://doi.org/10.1109/NOCS.2009.5071476

  • El-Moursy M and Friedman E. (2004). Optimum wire sizing of RLC interconnect with repeaters. Integration, the VLSI Journal. 38:2. (205-225). Online publication date: 1-Dec-2004.

    https://doi.org/10.1016/j.vlsi.2004.04.001

  • Hong X, Jing T, Xu J, Bao H and Gu J. (2003). CNB. Journal of Computer Science and Technology. 18:6. (732-738). Online publication date: 1-Nov-2003.

    https://doi.org/10.1007/BF02945461

  • Xu J, Hong X, Jing T, Cai Y and Gu J. (2003). An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integration, the VLSI Journal. 35:2. (69-84). Online publication date: 1-Aug-2003.

    https://doi.org/10.1016/S0167-9260(03)00029-4

  • Jing T, Hong X, Bao H, Cai Y, Xu J, Cheng C and Gu J. UTACO. Proceedings of the 2003 Asia and South Pacific Design Automation Conference. (834-839).

    https://doi.org/10.1145/1119772.1119956

  • Xu J, Hong X, Jing T, Cai Y and Gu J. An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. Proceedings of the 2002 Asia and South Pacific Design Automation Conference.

    /doi/10.5555/832284.835429