Al-Assadi W and Kakarla S. A BIST Technique for Crosstalk Noise Detection in FPGAs. Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems. (167-175).

Kakarla S and Al-Assadi W. (2007). A Framework for the Detection of Crosstalk Noise in FPGAs 2007 IEEE Region 5 Technical Conference. 10.1109/TPSD.2007.4380383. 978-1-4244-1279-2. (211-216).

http://ieeexplore.ieee.org/document/4380383/

Alpert C, Hu J, Sapatnekar S and Villarrubia P. (2006). A practical methodology for early buffer and wire resource allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:5. (573-583). Online publication date: 1-Nov-2006.

https://doi.org/10.1109/TCAD.2003.810749

Kastner R, Bozorgzadeh E and Sarrafzadeh M. (2006). Pattern routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:7. (777-790). Online publication date: 1-Nov-2006.

https://doi.org/10.1109/TCAD.2002.1013891

Alpert C, Gandham G, Hu J, Neves J, Quay S and Sapatnekar S. (2006). Steiner tree optimization for buffers, blockages, and bays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20:4. (556-562). Online publication date: 1-Nov-2006.

https://doi.org/10.1109/43.918213

Smey R, Swartz B and Madden P. Crosstalk Reduction in Area Routing. Proceedings of the conference on Design, Automation and Test in Europe - Volume 1.

/doi/10.5555/789083.1022832

Smey R, Swartz B and Madden P. Crosstalk reduction in area routing 6th Design Automation and Test in Europe (DATE 03). 10.1109/DATE.2003.1253714. 0-7695-1870-2. (862-867).

http://ieeexplore.ieee.org/document/1253714/

Hu J and Sapatnekar S. (2001). A survey on multi-net global routing for integrated circuits. Integration. 10.1016/S0167-9260(01)00020-7. 31:1. (1-49). Online publication date: 1-Nov-2001.

https://linkinghub.elsevier.com/retrieve/pii/S0167926001000207