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  • Chowdhury M, Hasan M, Hoque T and Hasan M. (2024). Physically Unclonable and Reconfigurable Circuits for IP Protection: Opportunities and Challenges 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 10.1109/ISVLSI61997.2024.00162. 979-8-3503-5411-9. (817-820).

    https://ieeexplore.ieee.org/document/10682723/

  • Wang Z, Alrahis L, Mankali L, Knechtel J and Sinanoglu O. (2024). LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 10.1109/ISVLSI61997.2024.00076. 979-8-3503-5411-9. (385-390).

    https://ieeexplore.ieee.org/document/10682661/

  • Tehranipoor M, Zamiri Azar K, Asadizanjani N, Rahman F, Mardani Kamali H and Farahmandi F. (2024). Advances in Logic Locking. Hardware Security. 10.1007/978-3-031-58687-3_2. (53-142).

    https://link.springer.com/10.1007/978-3-031-58687-3_2

  • Rai S and Kumar A. (2024). Polymorphic Primitives for Hardware Security. Design Automation and Applications for Emerging Reconfigurable Nanotechnologies. 10.1007/978-3-031-37924-6_7. (145-174).

    https://link.springer.com/10.1007/978-3-031-37924-6_7

  • Rai S and Kumar A. (2024). Physical Synthesis Flow and Liberty Generation. Design Automation and Applications for Emerging Reconfigurable Nanotechnologies. 10.1007/978-3-031-37924-6_6. (119-144).

    https://link.springer.com/10.1007/978-3-031-37924-6_6

  • Rai S and Kumar A. (2024). Introduction. Design Automation and Applications for Emerging Reconfigurable Nanotechnologies. 10.1007/978-3-031-37924-6_1. (1-24).

    https://link.springer.com/10.1007/978-3-031-37924-6_1

  • SLPSK P, Ray S and Bhunia S. TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs. IEEE Transactions on Computers. 10.1109/TC.2023.3248269. 72:8. (2306-2320).

    https://ieeexplore.ieee.org/document/10050826/

  • Trommer J, Bhattacharjee N, Mikolajick T, Huhn S, Merten M, Djeridane M, Hassan M, Drechsler R, Rai S, Kavand N, Darjani A, Kumar A, Sessi V, Drescher M, Kolodinski S and Wiatr M. (2023). Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). 10.23919/DATE56975.2023.10136918. . (1-6).

    https://ieeexplore.ieee.org/document/10136918/

  • Xu J, He J, Zhang J, Yang D, Wu J and Mao X. Validating the Redundancy Assumption for HDL from Code Clone's Perspective. Proceedings of the 2023 International Symposium on Physical Design. (247-255).

    https://doi.org/10.1145/3569052.3571872

  • Fei W, Trommer J, Lemme M, Mikolajick T and Heinzig A. (2022). Emerging reconfigurable electronic devices based on two‐dimensional materials: A review. InfoMat. 10.1002/inf2.12355. 4:10. Online publication date: 1-Oct-2022.

    https://onlinelibrary.wiley.com/doi/10.1002/inf2.12355

  • Venkataraman A, Amadi E and Papadopoulos C. (2022). Molecular-Scale Hardware Encryption Using Tunable Self-Assembled Nanoelectronic Networks. Micro. 10.3390/micro2030024. 2:3. (361-368).

    https://www.mdpi.com/2673-8023/2/3/24

  • Quijada J, Baldauf T, Rai S, Heinzig A, Kumar A, Weber W, Mikolajick T and Trommer J. A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation. IEEE Transactions on Nanotechnology. 10.1109/TNANO.2022.3221836. (1-8).

    https://ieeexplore.ieee.org/document/9947333/

  • Krinke A, Rai S, Kumar A and Lienig J. (2021). Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 10.1109/ICCAD51958.2021.9643439. 978-1-6654-4507-8. (1-9).

    https://ieeexplore.ieee.org/document/9643439/

  • Botero U, Wilson R, Lu H, Rahman M, Mallaiyan M, Ganji F, Asadizanjani N, Tehranipoor M, Woodard D and Forte D. (2021). Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspectives. ACM Journal on Emerging Technologies in Computing Systems. 17:4. (1-53). Online publication date: 31-Oct-2021.

    https://doi.org/10.1145/3464959

  • Japa A, Majumder M, Sahoo S and Vaddi R. (2021). Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things. International Journal of Circuit Theory and Applications. 10.1002/cta.3030. 49:8. (2299-2311). Online publication date: 1-Aug-2021.

    https://onlinelibrary.wiley.com/doi/10.1002/cta.3030

  • Raitza M, Marcker S, Trommer J, Heinzig A, Kluppelholz S, Baier C and Kumar A. Quantitative Characterization of Reconfigurable Transistor Logic Gates. IEEE Access. 10.1109/ACCESS.2020.3001352. 8. (112598-112614).

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