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- research-articleOctober 2008
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systemsOctober 2008, Pages 1–10https://doi.org/10.1145/1450095.1450099Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given that most wearout mechanisms that plague semiconductor ...
- ArticleDecember 2007
Self-calibrating Online Wearout Detection
MICRO 40: Proceedings of the 40th Annual IEEE/ACM International Symposium on MicroarchitectureDecember 2007, Pages 109–122https://doi.org/10.1109/MICRO.2007.37Technology scaling, characterized by decreasing feature size, thin- ning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology gener- ations. Physical analysis of device failure ...
- articleMarch 2007
Architecting a reliable CMP switch architecture
- Kypros Constantinides,
- Stephen Plaza,
- Jason Blome,
- Valeria Bertacco,
- Scott Mahlke,
- Todd Austin,
- Bin Zhang,
- Michael Orshansky
ACM Transactions on Architecture and Code Optimization (TACO), Volume 4, Issue 1Pages 2–eshttps://doi.org/10.1145/1216544.1216545As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are addressed, ...
- ArticleOctober 2006
Cost-efficient soft error protection for embedded microprocessors
CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systemsOctober 2006, Pages 421–431https://doi.org/10.1145/1176760.1176811Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds ...
- articleAugust 2006
The Liberty Simulation Environment: A deliberate approach to high-level system modeling
ACM Transactions on Computer Systems (TOCS), Volume 24, Issue 3Pages 211–249https://doi.org/10.1145/1151690.1151691In digital hardware system design, the quality of the product is directly related to the number of meaningful design alternatives properly considered. Unfortunately, existing modeling methodologies and tools have properties which make them less than ...
- ArticleMay 2005
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
ISCA '05: Proceedings of the 32nd annual international symposium on Computer ArchitectureJune 2005, Pages 272–283https://doi.org/10.1109/ISCA.2005.9Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency ...
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ACM SIGARCH Computer Architecture News: Volume 33 Issue 2, May 2005 - ArticleDecember 2004
RIFLE: An Architectural Framework for User-Centric Information-Flow Security
- Neil Vachharajani,
- Matthew J. Bridges,
- Jonathan Chang,
- Ram Rangan,
- Guilherme Ottoni,
- Jason A. Blome,
- George A. Reis,
- Manish Vachharajani,
- David I. August
MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on MicroarchitectureDecember 2004, Pages 243–254https://doi.org/10.1109/MICRO.2004.31Even as modern computing systems allow the manipulation and distribution of massive amounts of information, users of these systems are unable to manage the confidentiality of their data in a practical fashion. Conventional access control security ...
- articleMarch 2004
The Liberty Simulation Environment, version 1.0
ACM SIGMETRICS Performance Evaluation Review (SIGMETRICS), Volume 31, Issue 4March 2004, Pages 19–24https://doi.org/10.1145/1054907.1054912High-level hardware modeling via simulation is an essential step in hardware systems design and research. Despite the importance of simulation, current model creation methods are error prone and are unnecessarily time consuming. To address these ...
- ArticleJune 2003
The liberty simulation environment as a pedagogical tool
WCAE '03: Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer ArchitectureJune 2003, Pages 12–eshttps://doi.org/10.1145/1275521.1275538This paper describes how the Liberty Simulation Environment (LSE) and its graphical visualizer can be used in a computer architecture course. LSE allows for the rapid construction of simulators from models that resemble the structure of hardware. By ...
- ArticleNovember 2002
Microarchitectural exploration with Liberty
MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on MicroarchitectureNovember 2002, Pages 271–282To find the best designs, architects must rapidly simulate many design alternatives and have confidence in the results. Unfortunately, the most prevalent simulator construction methodology, hand-writing monolithic simulators in sequential programming ...