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- research-articleNovember 2015
Simulating stencil-based application on future Xeon Phi processor
PMBS '15: Proceedings of the 6th International Workshop on Performance Modeling, Benchmarking, and Simulation of High Performance Computing SystemsArticle No.: 7, Pages 1–10https://doi.org/10.1145/2832087.2832096An important application for hydrocarbon exploration is simulated on a performance model of a novel Intel architecture. The accuracy of the simulation models is demonstrated by correlating against an existing processor first and then against high-...
- research-articleDecember 2013
Using in-flight chains to build a scalable cache coherence protocol
- Samantika Subramaniam,
- Simon C. Steely,
- Will Hasenplaugh,
- Aamer Jaleel,
- Carl Beckmann,
- Tryggve Fossum,
- Joel Emer
ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, Issue 4Article No.: 28, Pages 1–24https://doi.org/10.1145/2541228.2541235As microprocessor designs integrate more cores, scalability of cache coherence protocols becomes a challenging problem. Most directory-based protocols avoid races by using blocking tag directories that can impact the performance of parallel ...
- chapterJanuary 2010
Multi core design for chip level multiprocessing
Advanced Lectures on Software EngineeringJanuary 2010, Pages 162–187Chip level integration continues to be a driving force in the computer industry. It lowers the cost and increases performance of computer systems, creating a remarkable rate of improvement in all processors, from handheld devices to supercomputers. ...
- ArticleAugust 2007
On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing
HOTI '07: Proceedings of the 15th Annual IEEE Symposium on High-Performance InterconnectsPage 4https://doi.org/10.1109/HOTI.2007.22There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some ...
- ArticleMarch 2004
Cache Scrubbing in Microprocessors: Myth or Necessity?
Transient faults from neutron and alpha particle strikes in large SRAM caches have become a major problem for microprocessor designers. To protect these caches, designers often use error correcting codes (ECC), which typically provide single-bit error ...