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- research-articleJanuary 2018
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 11, Issue 1Article No.: 3, Pages 1–23https://doi.org/10.1145/3158229We show that continuously monitoring on-chip delays at the LUT-to-LUT link level during operation allows a field-programmable gate array to detect and self-adapt to aging and environmental timing effects. Using a lightweight (<4% added area) mechanism ...
- research-articleOctober 2017
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs
- Ji Kim,
- Shunning Jiang,
- Christopher Torng,
- Moyang Wang,
- Shreesha Srinath,
- Berkin Ilbeyi,
- Khalid Al-Hawaj,
- Christopher Batten
MICRO-50 '17: Proceedings of the 50th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2017, Pages 759–773https://doi.org/10.1145/3123939.3136952Task-based parallel programming frameworks offer compelling productivity and performance benefits for modern chip multi-processors (CMPs). At the same time, CMPs also provide packed-SIMD units to exploit fine-grain data parallelism. Two fundamental ...
- tutorialDecember 2014
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on MicroarchitectureDecember 2014, Pages 75–87https://doi.org/10.1109/MICRO.2014.24Although GPGPUs are traditionally used to accelerate workloads with regular control and memory-access structure, recent work has shown that GPGPUs can also achieve significant speedups on more irregular algorithms. Data-driven implementations of ...
- research-articleJune 2013
Microarchitectural mechanisms to exploit value structure in SIMT architectures
ISCA '13: Proceedings of the 40th Annual International Symposium on Computer ArchitectureJune 2013, Pages 130–141https://doi.org/10.1145/2485922.2485934SIMT architectures improve performance and efficiency by exploiting control and memory-access structure across data-parallel threads. Value structure occurs when multiple threads operate on values that can be compactly encoded, e.g., by using a simple ...
Also Published in:
ACM SIGARCH Computer Architecture News: Volume 41 Issue 3, June 2013