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- surveySeptember 2022
A Survey on Assertion-based Hardware Verification
ACM Computing Surveys (CSUR), Volume 54, Issue 11sArticle No.: 225, Pages 1–33https://doi.org/10.1145/3510578Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and ...
- research-articleJanuary 2021
Directed Test Generation for Activation of Security Assertions in RTL Models
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 4Article No.: 26, Pages 1–28https://doi.org/10.1145/3441297Assertions are widely used for functional validation as well as coverage analysis for both software and hardware designs. Assertions enable runtime error detection as well as faster localization of errors. While there is a vast literature on both ...
- research-articleJanuary 2021
MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 3Article No.: 22, Pages 1–21https://doi.org/10.1145/3436820Detection of hardware Trojans is vital to ensure the security and trustworthiness of System-on-Chip (SoC) designs. Side-channel analysis is effective for Trojan detection by analyzing various side-channel signatures such as power, current, and delay. In ...
- research-articleJune 2020
Automated test generation for trojan detection using delay-based side channel analysis
DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in EuropePages 1031–1036Side-channel analysis is widely used for hardware Trojan detection in integrated circuits by analyzing various side-channel signatures, such as timing, power and path delay. Existing delay-based side-channel analysis techniques have two major bottlenecks:...
- research-articleJanuary 2020
Automated Test Generation for Activation of Assertions in RTL Models
ASPDAC '20: Proceedings of the 25th Asia and South Pacific Design Automation ConferencePages 223–228https://doi.org/10.1109/ASP-DAC47756.2020.9045731A major challenge in assertion-based validation is how to activate the assertions to ensure that they are valid. While existing test generation using model checking is promising, it cannot generate directed tests for large designs due to state space ...
- research-articleJanuary 2020
Automated Trigger Activation by Repeated Maximal Clique Sampling
ASPDAC '20: Proceedings of the 25th Asia and South Pacific Design Automation ConferencePages 482–487https://doi.org/10.1109/ASP-DAC47756.2020.9045449Hardware Trojans are serious threat to security and reliability of computing systems. It is hard to detect these malicious implants using traditional validation methods since an adversary is likely to hide them under rare trigger conditions. While ...
- doctoral_thesisJanuary 2020
Test Generation for System-On-Chip Security Validation
AbstractHardware security validation is crucial to ensure the integrity of System-on-Chip (SoC) designs. Attackers take advantage of SoC security vulnerabilities to inject malicious functionality into the design. Validation of SoC security is challenging ...
- research-articleJanuary 2019
Directed Test Generation for Validation of Cache Coherence Protocols
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 38, Issue 1Pages 163–176https://doi.org/10.1109/TCAD.2018.2801239Computing systems utilize multicore processors with complex cache coherence protocols to meet the increasing need for performance and energy improvement. It is a major challenge to verify the correctness of a cache coherence protocol since the number of ...