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- research-articleNovember 2024
AMD XDNA NPU in Ryzen AI Processors
- Alejandro Rico,
- Satyaprakash Pareek,
- Javier Cabezas,
- David Clarke,
- Baris Ozgul,
- Francisco Barat,
- Yao Fu,
- Stephan Münz,
- Dylan Stuart,
- Patrick Schlangen,
- Pedro Duarte,
- Sneha Date,
- Indrani Paul,
- Jian Weng,
- Sonal Santan,
- Vinod Kathail,
- Ashish Sirasao,
- Juanjo Noguera
The AMD Ryzen 7040 series is the first x86 processor with an integrated neural processing unit (NPU). The AMD XDNA technology in the NPU of Ryzen artificial intelligence (AI) processors provides optimized compute and memory resources for the needs for AI ...
- articleMarch 2014
Software-programmable digital pre-distortion on new generation FPGAs
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 78, Issue 3Pages 573–587https://doi.org/10.1007/s10470-013-0200-1In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded ...
- research-articleFebruary 2014
OmpSs@Zynq all-programmable SoC ecosystem
- Antonio Filgueras,
- Eduard Gil,
- Daniel Jimenez-Gonzalez,
- Carlos Alvarez,
- Xavier Martorell,
- Jan Langer,
- Juanjo Noguera,
- Kees Vissers
FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arraysPages 137–146https://doi.org/10.1145/2554688.2554777OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-...
- articleDecember 2011
Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 69, Issue 2-3Pages 119–129https://doi.org/10.1007/s10470-011-9765-8In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and ...
- ArticleSeptember 2011
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs
FPL '11: Proceedings of the 2011 21st International Conference on Field Programmable Logic and ApplicationsPages 103–109https://doi.org/10.1109/FPL.2011.28In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA ...
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- research-articleApril 2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 30, Issue 4Pages 473–491https://doi.org/10.1109/TCAD.2011.2110592Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we ...
- research-articleFebruary 2011
A Model-Based Approach to Cognitive Radio Design
IEEE Journal on Selected Areas in Communications (JSAC), Volume 29, Issue 2Pages 455–468https://doi.org/10.1109/JSAC.2011.110217Cognitive radio is a promising technology for fulfilling the spectrum and service requirements of future wireless communication systems. Real experimentation is a key factor for driving research forward. However, the experimentation testbeds available ...
- research-articleSeptember 2010
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3, Issue 3Article No.: 18, Pages 1–30https://doi.org/10.1145/1839480.1839488Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. In an on-demand computing environment, a dynamically invoked application is assigned resources such as data bandwidth, configurable logic. The limited ...
- research-articleSeptember 2010
Iris: an architecture for cognitive radio networking testbeds
- Paul D. Sutton,
- Jörg Lotze,
- Hicham Lahlou,
- Suhaib A. Fahmy,
- Keith E. Nolan,
- Bariş Özgül,
- Thomas W. Rondeau,
- Juanjo Noguera,
- Linda E. Doyle
IEEE Communications Magazine (COMAG), Volume 48, Issue 9Pages 114–122https://doi.org/10.1109/MCOM.2010.5560595Iris is a software architecture for building highly reconfigurable radio networks. It has formed the basis for a wide range of dynamic spectrum access and cognitive radio demonstration systems presented at a number of international conferences between ...
- ArticleJuly 2010
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration
ISVLSI '10: Proceedings of the 2010 IEEE Annual Symposium on VLSIPages 190–194https://doi.org/10.1109/ISVLSI.2010.19Due to their their high flexibility and their increasing logic resources, FPGAs can be found in a wider application range as in recent years. But especially in application domains, where only a very restricted power budget is available, FPGAs still have ...
- ArticleNovember 2009
Development framework for implementing FPGA-based cognitive network nodes
This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture for hardware abstraction, an adaptive run-time system for managing cognition, and high level design tools for cognitive radio development. ...
- ArticleApril 2009
Generic Software Framework for Adaptive Applications on FPGAs
FCCM '09: Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing MachinesPages 55–62https://doi.org/10.1109/FCCM.2009.6Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining high performance with flexibility. While significant research has been ...
- ArticleSeptember 2008
Towards Novel Approaches in Design Automation for FPGA Power Optimization
The exploitation of reconfigurable architectures is currently increasing for high-performance applications e.g. signal processing systems. Until now however, general purpose processors are typically applied for lowpower applications partly due to the un-...
- ArticleJune 2007
Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures
DAC '07: Proceedings of the 44th annual Design Automation ConferencePages 771–776https://doi.org/10.1145/1278480.1278673Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited logic resources are customized ...
- research-articleJuly 2006
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 14, Issue 7Pages 730–739https://doi.org/10.1109/TVLSI.2006.878343In this paper, we propose a configuration-aware datapartitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs ...
- ArticleMarch 2006
Software-friendly HW/SW co-simulation: an industrial case study
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Designers' forumPages 100–105This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test their software with their own tools and environment using an accurate ...
- ArticleSeptember 2004
Power-Performance Trade-Offs for Reconfigurable Computing
CODES+ISSS '04: Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004Pages 116–121In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. We show that an efficient hardware-software partitioning algorithm is ...
- ArticleSeptember 2004
Power-performance trade-offs for reconfigurable computing
CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisPages 116–121https://doi.org/10.1145/1016720.1016751In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. We show that an efficient hardware-software partitioning algorithm is ...
- articleMay 2004
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS), Volume 3, Issue 2Pages 385–406https://doi.org/10.1145/993396.993404Dynamic scheduling for system-on-chip (SoC) platforms has become an important field of research due to the emerging range of applications with dynamic behavior (e.g., MPEG-4). Dynamically reconfigurable architectures are an interesting solution for this ...
- ArticleOctober 2003
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures
CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systemsPages 73–83https://doi.org/10.1145/951710.951722Dynamic scheduling for System-on-Chip (SoC) platforms has become an important field of research due to the emerging range of applications with dynamic behavior (e.g. MPEG-4). Dynamically reconfigurable architectures are an interesting solution for this ...
