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- research-articleJuly 2021
- research-articleOctober 2018
Verified three-way program merge
Proceedings of the ACM on Programming Languages (PACMPL), Volume 2, Issue OOPSLAArticle No.: 165, Pages 1–29https://doi.org/10.1145/3276535Even though many programmers rely on 3-way merge tools to integrate changes from different branches, such tools can introduce subtle bugs in the integration process. This paper aims to mitigate this problem by defining a semantic notion of conflict-...
- research-articleJune 2016
Cartesian hoare logic for verifying k-safety properties
PLDI '16: Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and ImplementationJune 2016, Pages 57–69https://doi.org/10.1145/2908080.2908092Unlike safety properties which require the absence of a “bad” program trace, k-safety properties stipulate the absence of a “bad” interaction between k traces. Examples of k-safety properties include transitivity, associativity, anti-symmetry, and ...
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ACM SIGPLAN Notices: Volume 51 Issue 6, June 2016 - research-articleJune 2014
Consolidation of queries with user-defined functions
PLDI '14: Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and ImplementationJune 2014, Pages 554–564https://doi.org/10.1145/2594291.2594305Motivated by streaming and data analytics scenarios where many queries operate on the same data and perform similar computations, we propose program consolidation for merging multiple user-defined functions (UDFs) that operate on the same input. Program ...
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ACM SIGPLAN Notices: Volume 49 Issue 6, June 2014 - articleOctober 2013
LLVMVF: A Generic Approach for Verification of Multicore Software
Journal of Electronic Testing: Theory and Applications (JELT), Volume 29, Issue 5October 2013, Pages 635–646https://doi.org/10.1007/s10836-013-5405-9Proliferation of multicore hardware boosted the need for verification of multicore software that is running on these hardware. Multicore software demands new verification techniques different from the ones used for sequential software. Many optimized ...
- research-articleOctober 2012
Generation of TLM testbenches using mutation testing
CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisOctober 2012, Pages 323–332https://doi.org/10.1145/2380445.2380498Testbench development is a major component of simulation based verification, which is the de-facto verification technique used in the industry. Verification of a TLM design is not complete without a measure of the effectiveness of its testbenches. We ...