Article

Design methodology for IRA codes

Authors:

Frank Kienle,

Norbert WehnAuthors Info & Claims

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Pages 459 - 462

Published: 27 January 2004 Publication History

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Abstract

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-Density Parity-Ceck (LDPC) codes and even outperform the recently introduced Turbo-Codes of current communication standards. IRA codes can be represented by a Tanner graph with arbitrary connections between nodes of given degrees. The implementation complexity of an IRA decoders is dominated by the randomness of these connections.In this paper we present for the first time an IRA decoder architecture which can process any given IRA code. We developed a joint graph-decoder design methodology to construct the Tanner graph of a given IRA code which can be efficiently processed by this decoder architecture without any RAM access conflicts. We show that these constructed IRA codes can outperform the UMTS Turbo-Codes.

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Cited By

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Brack TKienle FWehn NGielen G(2006)Disclosing the LDPC code decoder design spaceProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131539(200-205)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131539
Kienle FBrack TWehn N(2005)A Synthesizable IP Core for DVB-S2 LDPC Code DecodingProceedings of the conference on Design, Automation and Test in Europe - Volume 310.1109/DATE.2005.39(100-105)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.39

Design methodology for IRA codes
1. Mathematics of computing
  1. Information theory

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Published In

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

January 2004

957 pages

ISBN:0780381750

General Chair:
Masaharu Imai
Osaka University

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IEEE Press

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Published: 27 January 2004

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ASPDAC04

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IPSJ
SIGDA
IEICE

ASPDAC04: Asia and South Pacific Design Automation Conference 2004

January 27 - 30, 2004

Yokohama, Japan

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Brack TKienle FWehn NGielen G(2006)Disclosing the LDPC code decoder design spaceProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131539(200-205)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131539
Kienle FBrack TWehn N(2005)A Synthesizable IP Core for DVB-S2 LDPC Code DecodingProceedings of the conference on Design, Automation and Test in Europe - Volume 310.1109/DATE.2005.39(100-105)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.39

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Design and analysis of non-binary LDPC and IRA modulation codes

Rate-compatible IRA codes using quadratic congruential extension sequences and puncturing

Low-complexity interleaver design for turbo codes

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