Article

Low-power programmable routing circuitry for FPGAs

Authors:

James H. Anderson,

F. N. NajmAuthors Info & Claims

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Pages 602 - 609

https://doi.org/10.1109/ICCAD.2004.1382647

Published: 07 November 2004 Publication History

Abstract

We propose two new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power or sleep. High-speed mode provides similar power and performance to a traditional routing switch. In low-power mode, speed is curtailed in order to reduce power consumption. Our first switch design reduces leakage power consumption by 36-40% in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. Leakage power in sleep mode is 61% lower than in high-speed mode. A second switch design offers a 36% smaller area overhead and reduces leakage by 28-30% in low-power vs. high-speed mode. The proposed switch designs require only minor changes to a traditional routing switch, making them easy to incorporate into current FPGA interconnect. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. Specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.

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Cited By

Hioki MSekigawa TNakagawa TKoike HMatsumoto YKawanami TTsutsumi THutchings BBetz V(2013)Fully-functional FPGA prototype with fine-grain programmable body biasingProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435280(73-80)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435280
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Wang QGupta SAnderson JChow PCheung P(2009)Clock power reduction for virtex-5 FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508132(13-22)Online publication date: 24-Feb-2009
https://dl.acm.org/doi/10.1145/1508128.1508132
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Low-power programmable routing circuitry for FPGAs
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Information

Published In

cover image ACM Conferences

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

November 2004

913 pages

ISBN:0780387023

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 November 2004

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ICCAD04

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SIGDA

ICCAD04: The International Conference on Computer-Aided Design 2004

November 7 - 11, 2004

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Hioki MSekigawa TNakagawa TKoike HMatsumoto YKawanami TTsutsumi THutchings BBetz V(2013)Fully-functional FPGA prototype with fine-grain programmable body biasingProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435280(73-80)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435280
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Wang QGupta SAnderson JChow PCheung P(2009)Clock power reduction for virtex-5 FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508132(13-22)Online publication date: 24-Feb-2009
https://dl.acm.org/doi/10.1145/1508128.1508132
Anderson JNajm F(2009)Low-power programmable FPGA routing circuitryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201744317:8(1048-1060)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017443
Hu YLin YHe LTuan T(2008)Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retimingACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442613:2(1-29)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344426
Kawanami THioki MMatsumoto YTsutsumi TNakagawa TSekigawa TKoike H(2007)Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGAIEICE - Transactions on Information and Systems10.1093/ietisy/e90-d.12.1947E90-D:12(1947-1955)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1093/ietisy/e90-d.12.1947
Lin YHu YHe LRaghunat VNebel WStan MRaghunathan AHenkel JMarculescu D(2006)An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reductionProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165613(168-173)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165613
Nabaa GAzizi NNajm FSentovich E(2006)An adaptive FPGA architecture with process variation compensation and reduced leakageProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147069(624-629)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147069
Hu YLin YHe LTuan TSentovich E(2006)Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reductionProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147036(478-483)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147036
Chen DCong JXu J(2006)Optimal simultaneous module and multivoltage assignment for low powerACM Transactions on Design Automation of Electronic Systems10.1145/1142155.114216111:2(362-386)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.1145/1142155.1142161
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