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Efficient construction of binary moment diagrams for verifying arithmetic circuits

Authors:

Kiyoharu Hamaguchi,

Akihito Morita,

Shuzo YajimaAuthors Info & Claims

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Pages 78 - 82

Published: 01 December 1995 Publication History

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Abstract

BDD-based approaches cannot handle some arithmetic functions such as multiplication efficiently, while Binary Moment Diagrams proposed by Bryant and Chen provide compact representations for those functions. They reported a BMD-based polynomial-time algorithm for verifying multipliers. This approach requires high-level information such as specifications to subcomponents. This paper presents a new technique called backward construction which can construct BMDs directly from circuit descriptions without any high-level information. The experiments show that the computation time for verifying for n-bit multipliers is approximately n^4. We have successfully verified 64-bit multipliers of several type in 3-6 hours with 40 Mbyte of memory on SPARCstation10/51. This result outperforms previous BDD-based approaches for verifying multipliers.

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Cited By

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Pellegrini ABertacco VAustin TDe Micheli GAl-Hashimi BMueller WMacii E(2010)Fault-based attack of RSA authenticationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871134(855-860)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871134
Krautz UWedler MKunz WWeber KJacobi CPflanz MKyung CChoi KHa S(2008)Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proofProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356902(398-403)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356902
(2008)Arithmetic Circuits Verification without Looking for Internal EquivalencesProceedings of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2008.4547681(7-16)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1109/MEMCOD.2008.4547681
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Index Terms

Efficient construction of binary moment diagrams for verifying arithmetic circuits
1. Hardware
  1. Hardware validation
    1. Functional verification

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ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

December 1995

748 pages

ISBN:0818672137

Chairman:
Richard Rudell
Synopsys, Inc., Mountain View, CA

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IEEE Computer Society

United States

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Published: 01 December 1995

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ICCAD '95: International Conference on Computer Aided Design

November 5 - 9, 1995

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Pellegrini ABertacco VAustin TDe Micheli GAl-Hashimi BMueller WMacii E(2010)Fault-based attack of RSA authenticationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871134(855-860)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871134
Krautz UWedler MKunz WWeber KJacobi CPflanz MKyung CChoi KHa S(2008)Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proofProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356902(398-403)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356902
(2008)Arithmetic Circuits Verification without Looking for Internal EquivalencesProceedings of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2008.4547681(7-16)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1109/MEMCOD.2008.4547681
Keim MDrechsler RBecker BMartin MMolitor P(2003)Polynomial Formal Verification of MultipliersFormal Methods in System Design10.1023/A:102175213039422:1(39-58)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.1023/A%3A1021752130394
Chang YTing KAckland B(2002)Self-referential verification of gate-level implementations of arithmetic circuitsProceedings of the 39th annual Design Automation Conference10.1145/513918.513998(311-316)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513998
Chang YCheng KErnst R(2001)Induction-based gate-level verification of multipliersProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603133(190-193)Online publication date: 4-Nov-2001
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Stoffel DKunz WErnst R(2001)Verification of integer multipliers on the arithmetic bit levelProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603132(183-189)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603132
Chen JChen YGoto S(2001)Equivalence checking of integer multipliersProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370315(169-174)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370315
Wefel SMolitor PSarrafzadeh MBanerjee PRoy K(2000)Prove that a faulty multiplier is faulty!?Proceedings of the 10th Great Lakes symposium on VLSI10.1145/330855.330957(43-46)Online publication date: 2-Mar-2000
https://dl.acm.org/doi/10.1145/330855.330957
Keim MMartin MBecker BDrechsler RMolitor P(1997)Polynomial Formal Verification of MultipliersProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836397Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836397
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A binary floating-point adder with the signed-digit number arithmetic

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A binary floating-point adder with the signed-digit number arithmetic

ACV: an arithmetic circuit verifier

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

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