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A unified approach to topology generation and area optimization of general floorplans

Published: 01 December 1995 Publication History

Abstract

In this paper, it is shown that for any rectangularly dualizable graph, a feasible topology can be obtained by using only either straight or Z-cutlines recursively within a bounding rectangle. Given an adjacency graph, a potential topology, which may be nonslicible and is likely to yield an optimally sized floorplan, is produced first in a top-down fashion using heuristic search in AND-OR graphs. The advantage of this technique is fourfold : (i) accelerates top-down search phase, (ii) generates a floorplan with minimal number of nonslice cores, (iii) ensures safe routing order without addition of pseudo-modules, and (iv) solves the bottom-up algorithm efficiently for optimal sizing of general floorplans in the second phase.

References

[1]
A. Bagchi and A. Mahanti, Admissible Heuristic Search in AND/OR Graphs, Theoretical Computer Science, 24, 1983, 207-219.
[2]
P.S. Dasgupta, S. Sur-Kolay and B.B. Bhattacharya, manuscript, 1995.
[3]
----, VLSI Floorplan Generation and Area Optimization using AND-OR Graph Search, Proc. 8th Intl. Conf. on VLSI Design, 1995, 370-375.
[4]
T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout Design, Wiley, 1990.
[5]
P. Pan and C.L. Liu, Area Minimization for Floorplans, IEEE TCAD, Vol. 14, No. 1, 1995, 123-132.
[6]
P. Pan, W. Shi, C.L. Liu, Area Minimization for Hierarchical Floorplans, Proc. ICCAD, 1994, 436-440.
[7]
S. Sur-Kolay and B.B. Bhattacharya, The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order, Proc. ICCD, 1991, 524-527.
[8]
----, On the family of Inherently Nonslicible Floorplans in VLSI Layout Design, Proc. ISCAS, June 1991, Singapore, 2850-2853.
[9]
----, Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning,Proc. DAC, June 1992, 69-74.
[10]
T.C. Wang and D.F. Wong, Optimal Floorplan Area Optimization, IEEE TCAD, Vol. 11, No. 8, 1992, 992- 1002.
[11]
K.H. Yeap and M. Sarrafzadeh, Sliceable Floorplanning by Graph Dualization, SIAM J. on Discrete Mathematics, May 1995.
[12]
----, A Unified Approach to Floorplan Sizing and Enumeration, IEEE TCAD, Vol. 12, No. 12, 1993, pp. 1858-67.

Cited By

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  • (1997)Hybrid floorplanning based on partial clustering and module restructuringProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244863(478-483)Online publication date: 1-Jan-1997
  • (1997)Slicibility of rectangular graphs and floorplan optimizationProceedings of the 1997 international symposium on Physical design10.1145/267665.267706(150-155)Online publication date: 1-Apr-1997

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cover image ACM Conferences
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
December 1995
748 pages
ISBN:0818672137

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IEEE Computer Society

United States

Publication History

Published: 01 December 1995

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Author Tags

  1. AND-OR graphs
  2. VLSI floorplanning
  3. heuristic search
  4. placement

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ICCAD '95
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ICCAD '95: International Conference on Computer Aided Design
November 5 - 9, 1995
California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (1997)Hybrid floorplanning based on partial clustering and module restructuringProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244863(478-483)Online publication date: 1-Jan-1997
  • (1997)Slicibility of rectangular graphs and floorplan optimizationProceedings of the 1997 international symposium on Physical design10.1145/267665.267706(150-155)Online publication date: 1-Apr-1997

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