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Test generation for multiple faults based on parallel vector pair analysis

Published: 07 November 1993 Publication History
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References

[1]
J. P. Roth, "Diagnosis of Automata Failures: A Calculus and a method," IBM J. Res. Develop., vol. 10, pp. 278-291, July 1966.
[2]
P. Goel, "Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," }{FEE Trans. on Comp., vol. C-30, pp. 215-222, Mar. 1981.
[3]
H. Fujiwara, and T. Shimono, "On the Acceleration on Test Generation Algorithms," IEEE Trans. on Comp., vol. C-32, pp. 1137-1144, Dec. 1983.
[4]
M. Schulz, and E. Auth, "Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques," FTCS-18, pp. 30-35, june 1988.
[5]
J. A. Waicukauski, P. A. Shul:~, D. J. Cfimmma, and A. Matin, "ATPG for Ultra- Large Structured Designs," 19901TC, pp. 44-51.~ Sept. 1990.
[6]
H. Cox, and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis," IEEE Trans. on CAD., vol. 7, pp. 813-833, July 1988.
[7]
J. Rajski, "Gemini - A Logic System for Fauk Diagnosis Based on Set Functions," FTCS-18, pp. 292-297, June 1988.
[8]
D. C. Bossen, and S. J. Hong, ",Cause-Effect Analysis for Multipk~ Fault Detection in Combinational Networks," IEEE Trans. on Comp., vol. C-20, pp. 1252-1257, Nov. 1971.
[9]
S. Kajihara, H. Shiba and K. Kinoshita, "Removal of Redundancy h~ Logic Circuits under Classification of Undetectable Faults," FTCS- 22, pp.263-270, July 1992.
[10]
R. Dandapani, and S. M. Reddy, "On the Design of Logic Networks with Redundancy and Testability Considerations," IEEE Trans. on Comp., vol. C-23, pp. 1139-1149, Nov. 1974.
[11]
S. Kajiham, I. Pomeranz, K. Kinoshita, and S. M. Reddy, "Cost- Effective Generation of Minirral Test Sets for Stuck-at Faults in Combinational Logic Circuits," 30th DAC, pp. 102-106, June 1993.
[12]
F. Brglez, and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Targq~ Translator in Fortran," ISCAS'85; Special Session on ATt~ and Fault Simulation, June 1985.
[13]
F. Brgl~z, D. Bryan, and K. Ko.zminstd, "Combinational Profiles of Sequential Benchmark Circuits," ISCAS'89, May 1989.

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  • (2019)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based DesignACM Transactions on Design Automation of Electronic Systems10.1145/332506624:4(1-19)Online publication date: 29-May-2019
  • (1997)Compact and complete test set generation for multiple stuck-faultsProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244559(212-219)Online publication date: 1-Jan-1997
  1. Test generation for multiple faults based on parallel vector pair analysis

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    cover image ACM Conferences
    ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
    November 1993
    781 pages
    ISBN:0818644907

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    Washington, DC, United States

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    Published: 07 November 1993

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    November 7 - 11, 1993
    California, Santa Clara, USA

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    • (2019)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based DesignACM Transactions on Design Automation of Electronic Systems10.1145/332506624:4(1-19)Online publication date: 29-May-2019
    • (1997)Compact and complete test set generation for multiple stuck-faultsProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244559(212-219)Online publication date: 1-Jan-1997

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