A logic simulation engine based on a modified data flow architecture
Pages 377 - 380
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Siegel, S., and M. E. Kaszynski, "The Design of a Logic Simulation Accelerator," VLSI Systems Design, Oct. 1985, pp. 76-80.
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Catlin, G. and B. Paseman, "Hardware Acceleration of Logic Simulation Using a Data Flow Architecture," Proc. of the ICCD," 1985.
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Denneau, M., "The Yorktown Simulation Engine," Proc. of the 19th DAC, 1982.
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Takasaki, S., et al., "HAL II: A Mixed Level Hardware Logic Simulation System," Proc. of the 23rd ACM/IEEE DAC, 1986, pp. 581-587.
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Saitoh, M., "Logic Simulation System Using Simulation Processor (SP)," Proc. of the 25th ACM~EEE DAC, 1988, pp. 225-230.
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Agrawal, P., "Architecture and Design of the MARS Hardware Accelerator," Proc. of the 24th ACM/IEEE DAC," 1987, pp. 101-107.
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- A logic simulation engine based on a modified data flow architecture
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Published: 08 November 1992
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