NOCS

On-chip shared memory is the primary paradigm for multi-core SoC designs and poses the most critical challenges to their scalability. Choosing the appropriate coherence model for accelerators not only can improve the overall system performance, but can ...

Networks-on-chip have become the standard interconnect solution to address the communication requirements of many-core chip multiprocessors. It is well-known that network performance and power consumption depend critically on the traffic load. The ...

High-performance interconnects need congestion control to deal with traffic bursts. In this paper, we propose ACCurate, a congestion control protocol that assigns exact max-min fair rates to flows, without relying on costly per-flow state inside the ...

Complex multicore Systems-on-Chips (SoCs) require large testing time and consume high amounts of power during post manufacturing test. With the advent of Network-on-Chip (NoC) based interconnections, the NoC has been envisioned to be reused as the Test ...

Silicon Photonics (SiPs) can overcome the energy and bandwidth limitations of electrical interconnects in networks-on-chip (NoCs) and enable efficient global all-to-all connectivity-the ideal from a performance perspective. Unfortunately, state-of-the-...

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free ...

High interconnect bandwidth is crucial to achieve better performance in many-core GPGPU architectures that execute highly data parallel applications. The parallel warps of threads running on shader cores generate a high volume of read requests to the ...

This paper introduces FreewayNoC, a Network-on-chip that routes packets at Dual Data Rate (DDR) and allows pipeline bypassing. Based on the observation that routers datapath is faster than control, a recent NoC design allowed flits to be routed at DDR ...

Deadlocks are a bane for network designers, be it a Network on Chip (NoC) in a multi-core or a large scale HPC/datacenter network. A routing deadlock occurs when there is a cyclic dependence between the buffers of network routers. Most modern systems ...

We set up a security analysis framework by aging the Network-on-Chip (NoC) to study planned obsolescence by the original equipment manufacturer (OEM). An NoC is the communication backbone in a manycore System-on-Chip (SoC). Planned obsolescence may ...

In modern Multi-Processors System-on-Chip (MP-SoC), it is highly desirable to provide hardware support for efficient multicast traffic. Recently, bufferless router has become a promising solution for NoC due to its simplicity and low overhead. However, ...

Packet based Network-on-Chip (NoC) connect tens to hundreds of components in a multi-core system. The routing and arbitration policies employed in traditional NoCs treat all application packets equally. However, some packets are critical as they stall ...

Wireless Network-on-Chip (WiNoC) is one of the most promising solutions to overcome multi-hop latency and high power consumption of modern many/multi core System-on-Chip (SoC). However, the design of efficient wireless links faces challenges to overcome ...

Timing channel attacks use interference from contending application flows to cause information leakage, and thereby either covertly transmit secrets, or create Denial-of-Service (DoS) attacks to undermine the on-chip hardware security. Protecting ...

The compact size and high wavelength selectivity of microring resonators (MRs) enable photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing (DWDM) in photonic waveguides to attain high bandwidth on-chip data transfers. A ...

With increasing integration in SoCs, the Network-on-Chip (NoC) connecting cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits to scaling of electrical wires in terms of energy and ...

All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores (referred to as bubbles) can be placed near active cores for ...

Parallel hardware accelerators for large-scale neural networks typically consist of several processing nodes, arranged as a multi- or many-core system-on-chip, connected by a network-on-chip (NoC). Recent proposals also benefit from the emerging 3D ...

Wireless Networks-on-Chip (WiNoC) are being explored for parallel applications to improve the performances by reducing the long distance/critical path communications. However, WiNoC still require precise propagation models to go beyond proof of concept ...

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and ...

Long range, low latency wireless links in Networks-on-Chip (NoCs) have been shown to be the most promising solution to provide high performance intra/inter-chip communication in many core era. Significant advancements have been made in design of both ...

The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition and data analytics), have driven the development of approximate computing circuits. Often as the most ...

The trend of unsustainable power cosumption and large memory bandwidth demands in massively parallel multicore systems, with the advent of the big data era, has brought upon the onset of alternate computation paradigms utilizing heterogeneity, ...

Distributed "edge" clouds provide the performance and security attributes to fill the cloud gap. The talk will cover the challenges and opportunities in bringing cloud to the comms infrastructure. "Edge Cloud" architectures are emerging as an area of ...

Network-on-Chip (NoC) is the dominant paradigm for on-chip interconnects. Two approaches for architecting a NoC can be distinguished. One is the generalization of bus-based interconnects inside a SoC, where transactions are associated with memory ...