research-article

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits

Authors:

Jeffrey Goeders,

Steven J. E. WiltonAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 36, Issue 1

Pages 83 - 96

https://doi.org/10.1109/TCAD.2016.2565204

Published: 01 January 2017 Publication History

Abstract

High-level synthesis (HLS) promises to increase designer productivity in the face of increasing field-programmable gate array sizes, and broaden the market of use, allowing software designers to reap the benefits of hardware implementation. One roadblock to HLS adoption is the lack of an in-system debugging infrastructure. Although designers can run their software code on a workstation, or simulate the register-transfer level, neither can reliably capture the behaviors, and therefore bugs, that may be present in the final system. Debugging hardware circuits in-system requires using signal-tracing to record circuit behavior for later offline analysis. In this paper, we present a debugging architecture, which automatically records key hardware signals, and relates them back to the original software source code. This architecture allows designers to debug HLS circuits in-system, in the context of the original source code. We present several signal-tracing techniques, tailored to HLS circuits, which allow a much longer execution trace to be captured. These techniques include signal compression, dynamically changing which signals are recorded cycle-by-cycle, and offline signal restoration. Compared to using an embedded logic analyzer to perform signal-tracing, our architecture increases the length of execution trace that can be recorded by 127X. For each 100 Kb of trace buffer memory, our architecture can record 15 369 executed lines of C code.

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Cited By

Attia SBetz V(2023)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-SimulationACM Transactions on Reconfigurable Technology and Systems10.1145/355252116:2(1-24)Online publication date: 10-May-2023
https://dl.acm.org/doi/10.1145/3552521
Vahdatniya PSharifian AHojabr RShriraman AKloeckner AMoreira J(2022)mu-grindProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569671(346-358)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569671
Attia SBetz V(2022)Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAsIEEE Transactions on Computers10.1109/TC.2021.313382871:10(2513-2526)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TC.2021.3133828
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 36, Issue 1

January 2017

183 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 January 2017

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Cited By

Attia SBetz V(2023)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-SimulationACM Transactions on Reconfigurable Technology and Systems10.1145/355252116:2(1-24)Online publication date: 10-May-2023
https://dl.acm.org/doi/10.1145/3552521
Vahdatniya PSharifian AHojabr RShriraman AKloeckner AMoreira J(2022)mu-grindProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569671(346-358)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569671
Attia SBetz V(2022)Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAsIEEE Transactions on Computers10.1109/TC.2021.313382871:10(2513-2526)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TC.2021.3133828
Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
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Valente GFanni TSau CMascio TPomante LPalumbo F(2021)A Composable Monitoring System for Heterogeneous Embedded PlatformsACM Transactions on Embedded Computing Systems10.1145/346164720:5(1-34)Online publication date: 9-Jul-2021
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Merlini MPoy IChow PShannon LAdler M(2021)Interactive Debugging at IP Block Interfaces in FPGAsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439305(138-144)Online publication date: 17-Feb-2021
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Sumeet NNambiar MBourcier JJiang ZBezemer CCortellessa V(2021)HLS_PRINT: High Performance Logging Framework on FPGAProceedings of the ACM/SPEC International Conference on Performance Engineering10.1145/3427921.3450238(145-152)Online publication date: 9-Apr-2021
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Murali AKakarla HAnitha Priyadarshini G(2021)Improved design debugging architecture using low power serial communication protocols for signal processing applicationsInternational Journal of Speech Technology10.1007/s10772-020-09784-x24:2(291-302)Online publication date: 1-Jun-2021
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Attia SBetz VNeuendorffer SShannon L(2020)StateMoverProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375307(175-185)Online publication date: 23-Feb-2020
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