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Optimus: efficient realization of streaming applications on FPGAs

Published: 19 October 2008 Publication History

Abstract

In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either software or hardware implementations. The compiler uses a hierarchical compilation strategy that separates concerns between macro- and micro-functional requirements. Macro-functional concerns address how components (modules) are assembled to implement larger more complex applications. Micro-functional issues deal with synthesis issues of the module internals. Optimus thus allows software developers who lack deep hardware design expertise to transparently leverage the advantages of hardware customization without crossing the semantic gap between high level languages and hardware description languages. Optimus generates streaming hardware that achieves on average 40x speedup over our baseline embedded processor for a fraction of the energy. Additionally, our results show that streaming-specific optimizations can further improve performance by 255% and reduce the area requirements by 16% in average. These designs are competitive with Handel-C implementations for some of the same benchmarks.

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  • (2023)Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators2023 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS58970.2023.10305451(1-7)Online publication date: 31-Oct-2023
  • (2023)The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image ProcessingJournal of Signal Processing Systems10.1007/s11265-023-01885-595:10(1181-1201)Online publication date: 29-Jul-2023
  • (2022)Optimizing data reshaping operations in functional IRs for high-level synthesisProceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3519941.3535069(61-72)Online publication date: 14-Jun-2022
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    cover image ACM Conferences
    CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
    October 2008
    274 pages
    ISBN:9781605584690
    DOI:10.1145/1450095
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 19 October 2008

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    Author Tags

    1. FPGA
    2. compiler
    3. embedded systems
    4. heterogeneous
    5. optimization
    6. streaming

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    ESWEEK 08
    ESWEEK 08: Fourth Embedded Systems Week
    October 19 - 24, 2008
    GA, Atlanta, USA

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    Overall Acceptance Rate 52 of 230 submissions, 23%

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    Cited By

    View all
    • (2023)Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators2023 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS58970.2023.10305451(1-7)Online publication date: 31-Oct-2023
    • (2023)The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image ProcessingJournal of Signal Processing Systems10.1007/s11265-023-01885-595:10(1181-1201)Online publication date: 29-Jul-2023
    • (2022)Optimizing data reshaping operations in functional IRs for high-level synthesisProceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3519941.3535069(61-72)Online publication date: 14-Jun-2022
    • (2022)Memory-Aware Functional IR for Higher-Level Synthesis of AcceleratorsACM Transactions on Architecture and Code Optimization10.1145/350176819:2(1-26)Online publication date: 31-Jan-2022
    • (2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
    • (2020)FleetProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378495(639-651)Online publication date: 9-Mar-2020
    • (2020)Predictive Compositional Method to Design and Reoptimize Complex Behavioral DataflowsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.296644739:10(2615-2627)Online publication date: Oct-2020
    • (2019)High-level synthesis of functional patterns with LiftProceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming10.1145/3315454.3329957(35-45)Online publication date: 8-Jun-2019
    • (2018)Stream Processing on Modern HardwareEncyclopedia of Database Systems10.1007/978-1-4614-8265-9_80758(3772-3776)Online publication date: 7-Dec-2018
    • (2017)Reusability is FIRRTL groundProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199728(209-216)Online publication date: 13-Nov-2017
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