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10.1145/1508128.1508189acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
poster

Performance and power of cache-based reconfigurable computing

Published: 22 February 2009 Publication History

Abstract

CHiMPS is a C-based compiler for high-performance computing (HPC) on heterogeneous CPU-FPGA computing platforms. CHiMPS efficiently supports random accesses to main memory through the many-cache memory model, enabling a broader range of applications to take advantage of FPGA-based acceleration. Many-cache creates multiple caches on top of an FGPA's small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. This poster presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches, and presents the details of the cache parameters on a Xilinx Virtex-5 LX110T FPGA. Detailed simulation results on HPC kernels demonstrate a 7.8x (geometric mean) performance boost over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater, by a geometric mean of 21.3x.

Cited By

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  • (2012)Automatic FPGA synthesis of memory intensive C-based kernels2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404167(136-143)Online publication date: Jul-2012
  • (2012)Configurable RTL model for level-1 cachesNORCHIP 201210.1109/NORCHP.2012.6403112(1-4)Online publication date: Nov-2012
  • (2012)Challenges and opportunities of ESL design automation2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology10.1109/ICSICT.2012.6467670(1-4)Online publication date: Oct-2012
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Published In

cover image ACM Conferences
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
February 2009
302 pages
ISBN:9781605584102
DOI:10.1145/1508128
  • General Chair:
  • Paul Chow,
  • Program Chair:
  • Peter Cheung

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2009

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Author Tags

  1. c-to-gates
  2. c-to-hardware
  3. caches
  4. co-processor accelerators
  5. fpga

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all
  • (2012)Automatic FPGA synthesis of memory intensive C-based kernels2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404167(136-143)Online publication date: Jul-2012
  • (2012)Configurable RTL model for level-1 cachesNORCHIP 201210.1109/NORCHP.2012.6403112(1-4)Online publication date: Nov-2012
  • (2012)Challenges and opportunities of ESL design automation2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology10.1109/ICSICT.2012.6467670(1-4)Online publication date: Oct-2012
  • (2012)Exploiting Memory-Level Parallelism in Reconfigurable AcceleratorsProceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2012.35(157-160)Online publication date: 29-Apr-2012
  • (2012)Memory-centric VDF graph transformations for practical FPGA implementation2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia10.1109/ESTIMedia.2012.6507023(12-18)Online publication date: Oct-2012

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