research-article

Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function

Authors:

Luciano A. de Lacerda,

Edson P. Santana,

Cleber Vinícius A. de Almeida,

Ana Isabela A. CunhaAuthors Info & Claims

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

Article No.: 9, Pages 1 - 6

https://doi.org/10.1145/1601896.1601908

Published: 31 August 2009 Publication History

Get Access

Abstract

This work presents an adaptation to the definition of the Integral Nonlinear Function (INLF) for distortion analysis of analog multipliers. Up to this time distortion in two-input multipliers has been evaluated by applying a constant signal to one of the inputs and verifying the linearity of the response with respect to the other input. This method however proves to be ineffective for assuring undistorted multiplying operation. Moreover, the conventional procedures, involving noisy and extensive AC measurements or FFT computation, are time-consuming and cumbersome, particularly if both multiplier input signals are taken into account simultaneously. Current-mode CMOS analog multiplier designs are simulated and analyzed concerning distortion by means of the proposed figure of merit (2D-INFL) and through a conventional procedure.

References

[1]

Cerdeira, A., Estrada, M., Quintero, R., Flandre, D., Ortiz-Conde, A. and García Sánchez, F. J. New method for determination of harmonic distortion in SOI FD transistors. Solid-State Electronics, 46, (2002), 103--108.

Crossref

Google Scholar

[2]

García Sánchez, F. J., Ortiz-Conde, A., Finol, J. L., Salazar, R. B. and Salcedo, J. A. A minimal integral nonlinearity criterion to optimize the design of a new tanh/sinh-type bipolar transistor. IEEE Trans. Circuits and Systems -- I: Fundamental Theory and Applications, 49, (Aug. 2002), 1062--1070.

Crossref

Google Scholar

[3]

Salazar, R. B., Ortiz-Conde, A. and García Sánchez, F. J. A computationally efficient method for evaluating distortion in DG-MOSFETs. In Proceedings of the NSTI -- Nanotech 2007, vol. 3, (Santa Clara, May, 2006), 582--585.

Google Scholar

[4]

Wilamowski, B. M. VLSI Analog multiplier/divider circuit. In IEEE Proceedings of International Symposium on Industrial Electronics, vol. 2, (Coimbra, Jul. 1998), 493--496.

Crossref

Google Scholar

[5]

Tanno, K., Ishizuka, O. and Tang, Z. Four-quadrant CMOS current-mode multiplier independent of device parameters, IEEE Trans. Circuits and Systems -- II: Analog and Digital Signal Processing, 47, (May 2000), 473--477.

Crossref

Google Scholar

[6]

Machado, M. B., Cunha, A. I. A., Schneider, M. C. and Galup-Montoro, C. Transconductance-based CMOS analog multiplier. In Proceedings of International Northeast Workshop on Circuits and Systems, (Montréal, Jun. 2008), 377--380.

Crossref

Google Scholar

[7]

Prommee, P., Somdunyakanok, M., Kummgern, M. and Deijhan, K. Single low-supply current-mode CMOS analog multiplier circuit. In IEEE Proc. International Symposium on Communications and Information Technologies, (Bangkok, Sep. 2006), 1101--1104.

Crossref

Google Scholar

[8]

Han, G. and Sánchez-Sinencio, E. CMOS transconductance multipliers: a tutorial. In Trans. Circuits and Systems -- II: Analog and Digital Signal Processing, 45, (Dec. 1998), 1550--1563.

Google Scholar

[9]

Galup-Montoro, C., Schneider, M. C. and Cunha, A. I. A., "A current based MOSFET model for integrated circuit design," Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7--55, edited by E. Sánchez-Sinencio and A. Andreou, IEEE Press, 1999.

Google Scholar

[10]

Cunha, A. I. A., Schneider, M. C. and Galup-Montoro, C., "An MOS Transistor Model for Analog Circuit Design," IEEE J. Solid-State Circuits, vol. 33, pp. 1510--1519, Oct. 1998.

Crossref

Google Scholar

[11]

SMASH Circuit Simulator, Dolphin Integration, Meylan, France. Homepage: http://www.dolphin.fr.

Google Scholar

[12]

Kaplan, W., Advanced Calculus, 5th edition, Pearson -- Addison Wesley, 2003.

Google Scholar

[13]

Cerdeira, A. et al. The Integral Function Method: A new method to determine the non-linear harmonic distortion. In Proceedings of International Symposium on Microeletronics Technology and Devices No. 18 -- SBMICRO 2003, (São Paulo, Sep. 2003).

Google Scholar

Cited By

View all

Gonçalves Gde Andrade FSilva MFreire RPereira MSantana ECunha A(2021)On the distortion analysis of electronic analog multipliersAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153948140(153948)Online publication date: Oct-2021
https://doi.org/10.1016/j.aeue.2021.153948
Goncalves GSilva Mde Andrade FCardoso Fde Sousa ASantana ECunha A(2019)Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2019.8667570(17-20)Online publication date: Feb-2019
https://doi.org/10.1109/LASCAS.2019.8667570
Goncalves Gde Andrade FSilva Mde Sousa APereira MSantana ECunha A(2019)Using Two-Dimensional DC Characterization to Improve Distortion Level of Analog Multipliers2019 4th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT)10.1109/INSCIT.2019.8868724(1-6)Online publication date: Aug-2019
https://doi.org/10.1109/INSCIT.2019.8868724

Index Terms

Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function
1. Hardware
  1. Integrated circuits

Recommendations

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A fully balanced CMOS Variable Gain Amplifier (VGA) based on current-mode techniques suitable for high frequency applications and large signals is presented. The VGA consists of an analog multiplier, current gain stages, and resistive loads. A frequency ...
A Compact Four-Quadrant Floating-Gate MOS Multiplier

A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active ...
A new strategy to design low power translinear based CMOS analog multiplier
Abstract
This paper deals with a new method to design CMOS analog multiplier which operates in four quadrants. The main core of the proposed multiplier circuit consists of two common pairs of translinear loops which make a symmetrical ...
Graphical abstract

Display Omitted
Highlights
- A new method for designing of CMOS analog multiplier which operates in four quadrants.

Comments

Information & Contributors

Information

Published In

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

August 2009

325 pages

ISBN:9781605587059

DOI:10.1145/1601896

General Chair:
Ivan Saraiva
UFRN, Brazil
,
Program Chairs:
Renato Perez Ribas
UFRGS, Brazil
,
Calvin Plett
Carleton University, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 August 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

SBCCI '09

Sponsor:

SBC
SIGDA
SBMICRO

SBCCI '09: 22nd Symposium on Integrated Circuits and System Design

August 31 - September 3, 2009

Natal, Brazil

Acceptance Rates

SBCCI '09 Paper Acceptance Rate 50 of 119 submissions, 42%;

Overall Acceptance Rate 133 of 347 submissions, 38%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
126
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 22 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Gonçalves Gde Andrade FSilva MFreire RPereira MSantana ECunha A(2021)On the distortion analysis of electronic analog multipliersAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153948140(153948)Online publication date: Oct-2021
https://doi.org/10.1016/j.aeue.2021.153948
Goncalves GSilva Mde Andrade FCardoso Fde Sousa ASantana ECunha A(2019)Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2019.8667570(17-20)Online publication date: Feb-2019
https://doi.org/10.1109/LASCAS.2019.8667570
Goncalves Gde Andrade FSilva Mde Sousa APereira MSantana ECunha A(2019)Using Two-Dimensional DC Characterization to Improve Distortion Level of Analog Multipliers2019 4th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT)10.1109/INSCIT.2019.8868724(1-6)Online publication date: Aug-2019
https://doi.org/10.1109/INSCIT.2019.8868724
Goncalves Gde Andrade FRibeiro Hde Santana Soares SNassiffe ISantana ECunha A(2016)Distortion analysis of integrated analog multipliers: DC versus AC approaches2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2016.7451016(87-90)Online publication date: Feb-2016
https://doi.org/10.1109/LASCAS.2016.7451016

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A Compact Four-Quadrant Floating-Gate MOS Multiplier

A new strategy to design low power translinear based CMOS analog multiplier

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A Compact Four-Quadrant Floating-Gate MOS Multiplier

A new strategy to design low power translinear based CMOS analog multiplier

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations