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Logic partition orderings for multi-FPGA systems

Authors:

Gaetano BorrielloAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Pages 32 - 38

https://doi.org/10.1145/201310.201315

Published: 15 February 1995 Publication History

Abstract

One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We described the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.

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Cited By

Farooq UMehrez H(2021)Pre-Silicon Verification Using Multi-FPGA Platforms: A ReviewJournal of Electronic Testing10.1007/s10836-021-05929-1Online publication date: 23-Feb-2021
https://doi.org/10.1007/s10836-021-05929-1
Dickin DShannon L(2008)Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platformsProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580156(67-72)Online publication date: 2-Jul-2008
https://dl.acm.org/doi/10.1109/ASAP.2008.4580156
Vahid FEbeling C(1997)I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioningProceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays10.1145/258305.258309(27-34)Online publication date: 9-Feb-1997
https://dl.acm.org/doi/10.1145/258305.258309
Show More Cited By

Index Terms

Logic partition orderings for multi-FPGA systems
1. Hardware

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cover image ACM Conferences

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Copyright © 1995 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Farooq UMehrez H(2021)Pre-Silicon Verification Using Multi-FPGA Platforms: A ReviewJournal of Electronic Testing10.1007/s10836-021-05929-1Online publication date: 23-Feb-2021
https://doi.org/10.1007/s10836-021-05929-1
Dickin DShannon L(2008)Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platformsProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580156(67-72)Online publication date: 2-Jul-2008
https://dl.acm.org/doi/10.1109/ASAP.2008.4580156
Vahid FEbeling C(1997)I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioningProceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays10.1145/258305.258309(27-34)Online publication date: 9-Feb-1997
https://dl.acm.org/doi/10.1145/258305.258309
Johannes FPennino TYoffa E(1996)Partitioning of VLSI circuits and systemsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240535(83-87)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240535
Johannes F(1996)Partitioning of VLSI circuits and systems33rd Design Automation Conference Proceedings, 199610.1109/DAC.1996.545551(83-87)Online publication date: 1996
https://doi.org/10.1109/DAC.1996.545551
Hauck SBorriello G(1995)An evaluation of bipartitioning techniquesProceedings Sixteenth Conference on Advanced Research in VLSI10.1109/ARVLSI.1995.515634(383-402)Online publication date: 1995
https://doi.org/10.1109/ARVLSI.1995.515634

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