research-article

MO-pack: many-objective clustering for FPGA CAD

Authors:

Senthilkumar Thoravi Rajavel,

Ali AkogluAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 818 - 823

https://doi.org/10.1145/2024724.2024908

Published: 05 June 2011 Publication History

Abstract

Applications targeting FPGA integrated systems impose strict energy, channel width and delay constraints. We introduce the first many-objective clustering, MO-Pack, that targets these performance metrics concurrently. Detailed performance comparisons over state of the art clustering strategies targeting energy (P-T-VPack), delay (T-VPack), channel width (iRAC), and timing and routability (T-RPack) show that MO-Pack achieves its goals without increasing the logic area.

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Cited By

Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration10.1016/j.vlsi.2023.10209894(102098)Online publication date: Jan-2024
https://doi.org/10.1016/j.vlsi.2023.102098
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Elgammal MBetz V(2023)Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-ClusteringProceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3597031.3597054(11-18)Online publication date: 14-Jun-2023
https://dl.acm.org/doi/10.1145/3597031.3597054
Show More Cited By

Index Terms

MO-pack: many-objective clustering for FPGA CAD
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

Sponsor:

EDAC
SIGDA

DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration10.1016/j.vlsi.2023.10209894(102098)Online publication date: Jan-2024
https://doi.org/10.1016/j.vlsi.2023.102098
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Elgammal MBetz V(2023)Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-ClusteringProceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3597031.3597054(11-18)Online publication date: 14-Jun-2023
https://dl.acm.org/doi/10.1145/3597031.3597054
Lin ZXie YZou PWang SYu JChen J(2022)An Incremental Placement Flow for Advanced FPGAs With Timing AwarenessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312007041:9(3092-3103)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120070
Li ZMei YLin JZhu Z(2022)An Effective Routability-Driven Packing Algorithm for Large-Scale Heterogeneous FPGAs2022 IEEE 4th International Conference on Circuits and Systems (ICCS)10.1109/ICCS56666.2022.9936463(1-6)Online publication date: 23-Sep-2022
https://doi.org/10.1109/ICCS56666.2022.9936463
Bouaziz KChtourou SMarrakchi ZObeid AAbid M(2021)A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGAIntelligent Systems Design and Applications10.1007/978-3-030-71187-0_39(425-434)Online publication date: 3-Jun-2021
https://doi.org/10.1007/978-3-030-71187-0_39
Chen JLin ZKuo YHuang CChang YChen SChiang CKuo S(2020)Clock-Aware Placement for Large-Scale Heterogeneous FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.296889239:12(5042-5055)Online publication date: Dec-2020
https://doi.org/10.1109/TCAD.2020.2968892
Li WDehkordi MYang SPan DBazargan KNeuendorffer S(2019)Simultaneous Placement and Clock Tree Construction for Modern FPGAsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293897(132-141)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293897
Li WPan D(2019)A New Paradigm for FPGA Placement Without Explicit PackingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287701738:11(2113-2126)Online publication date: Nov-2019
https://doi.org/10.1109/TCAD.2018.2877017
Bouaziz KChtourou SMarrakchi ZAbid MObeid A(2019)Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188138(658-665)Online publication date: Jul-2019
https://doi.org/10.1109/HPCS48598.2019.9188138
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