Applying transactional memory to concurrency bugs
Pages 211 - 222
Abstract
Multithreaded programs often suffer from synchronization bugs such as atomicity violations and deadlocks. These bugs arise from complicated locking strategies and ad hoc synchronization methods to avoid the use of locks. A survey of the bug databases of major open-source applications shows that concurrency bugs often take multiple fix attempts, and that fixes often introduce yet more concurrency bugs. Transactional memory (TM) enables programmers to declare regions of code atomic without specifying a lock and has the potential to avoid these bugs. Where most previous studies have focused on using TM to write new programs from scratch, we consider its utility in fixing existing programs with concurrency bugs. We therefore investigate four methods of using TM on three concurrent programs. Overall, we find that 29% of the bugs are not fixable by transactional memory, showing that TM does not address many important types of concurrency bugs. In particular, TM works poorly with extremely long critical sections and with deadlocks involving both condition variables and I/O. Conversely, we find that for 56% of the bugs, transactional memory offers demonstrable value by simplifying the reasoning behind a fix or the effort to implement a fix, and using transactions in the first place would have avoided 71% of the bugs examined. We also find that ad hoc synchronization put in place to avoid the overhead of locking can be greatly simplified with TM, but requires hardware support to perform well.
References
[1]
The IBM Blue Gene/Q compute chip with SIMD floating-point unit. Hot Chips 23, Aug. 2011.
[2]
A.-R. Adl-Tabatabai and T. Shpeisman. Draft specification of transactional language constructs for C+, version 1.0. http://software.intel.com/file/21569, Aug. 2009.
[3]
AMD Corporation. Advanced synchronization facility: Proposed architectural specification, rev. 2.1. http://developer.amd.com/assets/45432-ASF_Spec_2.1.pdf, Mar. 2009.
[4]
L. Baugh and C. Zilles. An analysis of I/O and syscalls in critical sections and their implications for transactional memory. In Proc. of the 2nd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Aug. 2007.
[5]
C. Blundell, J. Devietti, E. C. Lewis, and M. M. Martin. Making the fast case common and the uncommon case simple in unbounded transactional memory. In Proc. of the 34th Annual Intnl. Symp. on Computer Architecture, June 2007.
[6]
C. Cascaval, C. Blundell, M. Michael, H. W. Cain, P. Wu, S. Chiras, and S. Chatterjee. Software transactional memory: Why is it only a research toy? Commun. ACM, 51(11):40--46, 2008.
[7]
S. Cherem, T. Chilimbi, and S. Gulwani. Inferring locks for atomic sections. In Proc. of the SIGPLAN 2008 Conf. on Programming Language Design and Implementation, June 2008.
[8]
L. Chew and D. Lie. Kivati: Fast detection and prevention of atomicity violations. In Proc. of the 5th ACM European Conf. on Computer Systems, Apr. 2010.
[9]
D. Christie, J.-W. Chung, S. Diestelhorst, M. Hohmuth, M. Pohlack, C. Fetzer, M. Nowack, T. Riegel, P. Felber, P. Marlier, and E. Riviere. Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack. In Proc. of the 5th ACM European Conf. on Computer Systems, Apr. 2010.
[10]
L. Dalessandro, F. Carouge, S. White, Y. Lev, M. Moir, M. L. Scott, and M. F. Spear. Hybrid NOrec: A case study in the effectiveness of best effort hardware transactional memory. In Proc. of the 16th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2011.
[11]
L. Dalessandro, M. L. Scott, and M. F. Spear. Transactions as the foundation of a memory consistency model. In Proc. of the 24th International Symp. on Distributed Computing, Sept. 2010.
[12]
L. Dalessandro, M. F. Spear, and M. L. Scott. NOrec: Streamlining S™ by abolishing ownership records. In Proc. of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Jan. 2010.
[13]
P. Damron, A. Fedorova, Y. Lev, V. Luchango, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proc. of the 12th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, Oct. 2006.
[14]
D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proc. of the 14th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2009.
[15]
D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proc. of the 20th International Symp. on Distributed Computing, Sept. 2006.
[16]
A. Dragojević, R. Guerraoui, and M. Kapalka. Stretching transactional memory. In Proc. of the SIGPLAN 2009 Conf. on Programming Language Design and Implementation, June 2009.
[17]
P. Dudnik and M. M. Swift. Condition variables and transactional memory: Problem or opportunity? In Proc. of the 4rd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Feb. 2009.
[18]
M. Emmi, J. S. Fischer, R. Jhala, and R. Majumdar. Lock allocation. In Proc. of the 34th ACM SIGPLAN/SIGACT Symp. on Principles of Programming Languages, 2007.
[19]
P. Felber, C. Fetzer, and T. Riegel. Dynamic performance tuning of word-based software transactional memory. In Proc. of the 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Feb. 2008.
[20]
L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proc. of the 31st Annual Intnl. Symp. on Computer Architecture, June 2004.
[21]
T. Harris, J. R. Larus, and R. Rajwar. Transactional Memory, 2nd edition. Morgan & Claypool Publishers, 2010.
[22]
T. Harris, S. Marlow, S. P. Jones, and M. Herlihy. Composable memory transactions. In Proc. of the 10th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, June 1991.
[23]
HIPEAC. Gcc for transactional memory. http://www.hipeac.net/node/2419.
[24]
Intel. Intel C+ S™ compiler, Prototype edition. http://software.intel.com/en-us/articles/intel-c-stm-compiler-prototype%-edition/, 2009.
[25]
G. Jin, L. Song, W. Zhang, S. Lu, and B. Liblit. Automated atomicity-violation fixing. In Proc. of the SIGPLAN 2011 Conf. on Programming Language Design and Implementation, June 2011.
[26]
H. Jula, D. M. Tralamazza, C. Zamfir, and G. Candea. Deadlock immunity: Enabling systems to defend against deadlocks. In Proc. of the 8th USENIX Symp. on Operating Systems Design and Implementation, Dec. 2008.
[27]
E. Koskinen and M. Herlihy. Dreadlocks: Efficient deadlock detection. In Proc. of the 20th ACM Symp. on Parallel Algorithms and Architectures, June 2008.
[28]
B. W. Lampson and D. D. Redell. Experience with processes and monitors in Mesa (summary). In Proc. of the 7th Symp. on Operating System Principles, Dec. 1979.
[29]
Y. Lev, M. Moir, and D. Nussbaum. Ph™: Phased transactional memory. In Proc. of the 2nd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Aug. 2007.
[30]
S. Lu, S. Park, E. Seo, and Y. Zhou. Learning from mistakes: A comprehensive study on real world concurrency bug characteristics. In Proc. of the 13th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2008.
[31]
B. Lucia, J. Devietti, K. Strauss, and L. Ceze. Atom-aid: Detecting and surviving atomicity violations. In Proc. of the 35th Annual Intnl. Symp. on Computer Architecture, June 2008.
[32]
M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News, pages 92--99, Sept. 2005.
[33]
B. McCloskey, F. Zhou, D. Gay, and E. Brewer. Autolocker: Synchronization inference for atomic sections. In Proc. of the 33rd ACM SIGPLAN/SIGACT Symp. on Principles of Programming Languages, 2006.
[34]
K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Logtm: Log-based transactional memory. In Proc. of the 12th IEEE Symp. on High-Performance Computer Architecture, Feb. 2006.
[35]
Mozilla. Performance: Page load and DHTML performance. http://wiki.mozilla.org/Performance:Home_Page, Mar. 2010.
[36]
Y. Ni, A. Welc, A.-R. Adl-Tabatabai, M. Bach, S. Berkowits, J. Cownie, R. Geva, S. Kozhukow, R. Narayanaswamy, J. Olivier, S. Preis, B. Saha, A. Tal, and X. Tian. Design and implementation of transactional constructs for c/c+. In Proc. of the 23rd SIGPLAN Conf. on Object-Oriented Programming, Systems, Languages and Application, Oct. 2008.
[37]
V. Pankratius. Does transactional memory keep its promises? Results from an empirical study. Technical Report 2009--12, University of Karlsruhe, Germany, Sept. 2009.
[38]
M. Pohlack and S. Diestelhorst. From lightweight hardware transactional memory to lightweight lock elision. In Proc. of the 6th ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, June 2011.
[39]
D. E. Porter, O. S. Hofmann, C. J. Rossbach, A. Benn, and E. Witchel. Operating systems transactions. In Proc. of the 22nd ACM Symp. on Operating System Principles, Oct. 2009.
[40]
F. Qin, J. Tucek, J. Sundaresan, and Y. Zhou. Rx: Treating bugs as allergies -- a safe method to survive software failure. In Proc. of the 20th ACM Symp. on Operating System Principles, Oct. 2005.
[41]
S. Rajamani, G. Ramalingam, V. P. Ranganath, and K. Vaswani. ISOLATOR: Dynamically ensuring isolation in concurrent programs. In Proc. of the 14th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2009.
[42]
R. Rajwar and J. R. Goodman. Transactional lock-free execution of lock-based programs. In Proc. of the 10th Intnl. Conf. on Architectural Support for Programming Languages and Operating Systems, 2002.
[43]
R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proc. of the 32nd Annual Intnl. Symp. on Computer Architecture, June 2005.
[44]
H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, and E. Witchel. Meta™/TxLinux: Transactional memory for an operating system. In Proc. of the 34th Annual Intnl. Symp. on Computer Architecture, June 2007.
[45]
C. J. Rossbach, O. S. Hofmann, D. E. Porter, H. E. Ramadan, A. Bhandari, and E. Witchel. TxLinux: Using and managing hardware transactional memory in an operating system. In Proc. of the 21st ACM Symp. on Operating System Principles, Oct. 2007.
[46]
C. J. Rossbach, O. S. Hofmann, and E. Witchel. Is transactional programming actually easier? In Proc. of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Jan. 2010.
[47]
A. Roy, S. Hand, and T. Harris. A runtime system for software lock elision. In Proc. of the 4th ACM European Conf. on Computer Systems, Apr. 2009.
[48]
B. Saha, A.-R. Adl-Tabatabai, R. L. Hudson, C. C. Minh, and B. Hertzberg. McRT-S™: A high performance software transactional memory system for a multi-core runtime. In Proc. of the 11th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Mar. 2006.
[49]
T. Shpeisman, A.-R. Adl-Tabatabai, R. Geva, Y. Ni, and A. Welc. Towards transactional memory semantics for C+. In Proc. of the 21st ACM Symp. on Parallel Algorithms and Architectures, June 2009.
[50]
M. F. Spear, M. Silverman, L. Dalessandro, M. M. Michael, and M. L. Scott. Implementing and exploiting inevitability in software transactional memory. In Proc. of the 37th Intnl. Conf. on Parallel Processing, Sept. 2008.
[51]
M. M. Swift, H. Volos, N. Goyal, L. Yen, M. D. Hill, and D. A. Wood. OS support for virtualizing hardware transactional memory. In Proc. of the 3rd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Feb. 2008.
[52]
T. Usui, Y. Smaragdakis, and R. Behrends. Adaptive locks: Combining transactions and locks for efficient concurrency. In Proc. of the 4rd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Feb. 2009.
[53]
H. Volos, N. Goyal, and M. M. Swift. Pathological interaction of locks with transactional memory. In Proc. of the 3rd ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, Feb. 2008.
[54]
H. Volos, A. J. Tack, N. Goyal, M. M. Swift, and A. Welc. xCalls: Safe I/O in memory transactions. In Proc. of the 4th ACM European Conf. on Computer Systems, Apr. 2009.
[55]
Webkit. Sunspider javascript benchmark. http://www2.webkit.org/perf/sunspider-0.9/sunspider.html.
[56]
A. Welc, B. Saha, and A.-R. Adl-Tabatabai. Irrevocable transactions and their applications. In Proc. of the 20th ACM Symp. on Parallel Algorithms and Architectures, June 2008.
[57]
H. Wettstein. The problem of nested monitor calls revisited. SIGOPS Operating Systems Review, January 1978.
[58]
W. Xiong, S. Park, J. Zhang, Y. Zhou, and Z. Ma. Ad hoc synchronization considered harmful. In Proc. of the 9th USENIX Symp. on Operating Systems Design and Implementation, Oct. 2010.
[59]
L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In Proc. of the 13th IEEE Symp. on High-Performance Computer Architecture, Feb. 2007.
[60]
F. Zyulkyarov, V. Gajinov, O. S. Unsal, A. Cristal, E. Ayguadé, T. Harris, and M. Valero. Atomic Quake: Using transactional memory in an interactive multiplayer game server. In Proc. of the 14th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Feb. 2009.
Index Terms
- Applying transactional memory to concurrency bugs
Recommendations
Applying transactional memory to concurrency bugs
ASPLOS XVII: Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating SystemsMultithreaded programs often suffer from synchronization bugs such as atomicity violations and deadlocks. These bugs arise from complicated locking strategies and ad hoc synchronization methods to avoid the use of locks. A survey of the bug databases of ...
Applying transactional memory to concurrency bugs
ASPLOS '12Multithreaded programs often suffer from synchronization bugs such as atomicity violations and deadlocks. These bugs arise from complicated locking strategies and ad hoc synchronization methods to avoid the use of locks. A survey of the bug databases of ...
AVIO: detecting atomicity violations via access interleaving invariants
ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systemsConcurrency bugs are among the most difficult to test and diagnose of all software bugs. The multicore technology trend worsens this problem. Most previous concurrency bug detection work focuses on one bug subclass, data races, and neglects many other ...
Comments
Information & Contributors
Information
Published In
March 2012476 pages
Copyright © 2012 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 03 March 2012
Published in SIGARCH Volume 40, Issue 1
Check for updates
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations21Total Citations
- 692Total Downloads
- Downloads (Last 12 months)15
- Downloads (Last 6 weeks)1
Reflects downloads up to 22 Sep 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in