research-article

A low-overhead interconnect architecture for virtual reconfigurable fabrics

Authors:

Greg StittAuthors Info & Claims

CASES '12: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems

Pages 111 - 120

https://doi.org/10.1145/2380403.2380427

Published: 07 October 2012 Publication History

Abstract

Field-programmable gate arrays (FPGAs) have been widely shown to have significant performance and power advantages compared to microprocessors and graphics-processing units (GPUs), but remain a niche technology due in part to productivity challenges. Although such challenges have numerous causes, previous work has shown two significant contributing factors: 1) prohibitive place-and-route times preventing mainstream design methodologies, and 2) limited application portability preventing design reuse. Virtual reconfigurable architectures, referred to as intermediate fabrics (IFs), were recently introduced as a potential solution to these problems, providing 100x-1000x place-and-route speedup, while also enabling application portability across potentially any physical FPGA. However, one significant limitation of existing intermediate fabrics is area overhead incurred from virtualized interconnect resources. In this paper, we perform design-space exploration of virtual interconnect architectures and introduce an optimized virtual interconnect that reduces area overhead by 48% to 54% compared to previous work, while also improving clock frequencies by 24% with a modest routability overhead of 16%.

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Cited By

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https://dl.acm.org/doi/10.1145/3447970
Ijaz QBourennane EBashir AAsghar H(2020)Revisiting the High-Performance Reconfigurable Computing for Future DatacentersFuture Internet10.3390/fi1204006412:4(64)Online publication date: 6-Apr-2020
https://doi.org/10.3390/fi12040064
Kourfali AFricke FHuebner MStroobandt D(2019)An Integrated on-Silicon Verification Method for FPGA OverlaysJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05786-z35:2(173-189)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10836-019-05786-z
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Index Terms

A low-overhead interconnect architecture for virtual reconfigurable fabrics
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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cover image ACM Conferences

CASES '12: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems

October 2012

230 pages

ISBN:9781450314244

DOI:10.1145/2380403

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Vincent Mooney
Georgia Institute of Technology, USA
,
Rodric Rabbah
IBM, USA

Copyright © 2012 ACM.

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Published: 07 October 2012

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Cited By

Charitopoulos GPnevmatikatos DGaydadjiev G(2021)MC-DeFACM Transactions on Architecture and Code Optimization10.1145/344797018:3(1-25)Online publication date: 14-Apr-2021
https://dl.acm.org/doi/10.1145/3447970
Ijaz QBourennane EBashir AAsghar H(2020)Revisiting the High-Performance Reconfigurable Computing for Future DatacentersFuture Internet10.3390/fi1204006412:4(64)Online publication date: 6-Apr-2020
https://doi.org/10.3390/fi12040064
Kourfali AFricke FHuebner MStroobandt D(2019)An Integrated on-Silicon Verification Method for FPGA OverlaysJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05786-z35:2(173-189)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10836-019-05786-z
Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Vaishnav APham KKoch D(2018)A Survey on FPGA Virtualization2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00031(131-1317)Online publication date: Aug-2018
https://doi.org/10.1109/FPL.2018.00031
Jain AMaskell DFahmy SFanucci LTeich J(2016)Throughput oriented FPGA overlays using DSP blocksProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972187(1628-1633)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972187
Jain ALi XFahmy SMaskell D(2016)Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx ZynqACM SIGARCH Computer Architecture News10.1145/2927964.292797043:4(28-33)Online publication date: 22-Apr-2016
https://dl.acm.org/doi/10.1145/2927964.2927970
Jain ALi XSinghai PMaskell DFahmy S(2016)DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2016.10(1-8)Online publication date: May-2016
https://doi.org/10.1109/FCCM.2016.10
Jain AMaskell DFahmy S(2016)Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech)10.1109/DASC-PICom-DataCom-CyberSciTec.2016.110(586-593)Online publication date: Aug-2016
https://doi.org/10.1109/DASC-PICom-DataCom-CyberSciTec.2016.110
Cooke PHao LStitt G(2015)Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application PortabilityACM Transactions on Embedded Computing Systems10.1145/270008214:3(1-25)Online publication date: 21-Apr-2015
https://dl.acm.org/doi/10.1145/2700082
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