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Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only)

Published: 22 February 2015 Publication History

Abstract

This paper presents an optimized fixed-point implementation of space-vector pulse-width modulation (SVPWM) for a two-level inverter. Bit-width fixed-point signals as well as circuit area are minimized by meeting the desired design accuracy. Most of the designs currently available are specified in floating-point precision to speed the process of simulating their functionality. However, area-optimized hardware implementation of these algorithms requires fixed-point precision. A generic function is used to formulate the precision required for each signal to get the proper accuracy. A non-convex optimization problem is solved for the number of required bit-widths for the signals. This solution has been simulated and implemented on FPGA to verify the resulting accuracy.

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cover image ACM Conferences
FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 2015
292 pages
ISBN:9781450333153
DOI:10.1145/2684746
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2015

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Author Tags

  1. fixed-point
  2. fpga
  3. simulated annealing
  4. svpwm

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FPGA '15
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FPGA '15 Paper Acceptance Rate 20 of 102 submissions, 20%;
Overall Acceptance Rate 125 of 627 submissions, 20%

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