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STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems

Published: 09 September 2015 Publication History

Abstract

This article introduces STM-HRT, a nonblocking wait-free software transactional memory (STM) for hard real-time (HRT) multicore embedded systems. Resource access control in HRT systems is usually implemented with lock-based synchronization. However, these mechanisms may lead to deadlocks or starvations and do not scale well with the number of cores. Most existing nonblocking STM are not suitable for HRT systems, because it is not possible to find an upper bound of the execution time for each task. In this article, we show how STM-HRT can be a robust solution for resource sharing in HRT multicore systems. We provide a detailed description of STM-HRT architecture. We propose a set of arguments to establish the functional correctness of its concurrency control protocol. Finally, as part of a real-time analysis, we derive upper bounds on the computations required to access shared data under STM-HRT.

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Cited By

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  • (2021)TORTIS: Retry-Free Software Transactional Memory for Real-Time Systems2021 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS52674.2021.00049(469-481)Online publication date: Dec-2021
  • (2020)Analysis of Polka Contention Manager for use in Multicore Hard Real-Time SystemsProceedings of the 28th International Conference on Real-Time Networks and Systems10.1145/3394810.3394825(11-21)Online publication date: 9-Jun-2020
  • (2019)Practical Progress Verification of Descriptor-Based Non-Blocking Data Structures2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2019.00019(83-93)Online publication date: Oct-2019

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  1. STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems

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    Published In

    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 14, Issue 4
    December 2015
    604 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/2821757
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 09 September 2015
    Accepted: 01 May 2015
    Revised: 01 February 2015
    Received: 01 September 2014
    Published in TECS Volume 14, Issue 4

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    Author Tags

    1. Hard real time
    2. embedded systems
    3. nonblocking synchronization
    4. software transactional memory

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    View all
    • (2021)TORTIS: Retry-Free Software Transactional Memory for Real-Time Systems2021 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS52674.2021.00049(469-481)Online publication date: Dec-2021
    • (2020)Analysis of Polka Contention Manager for use in Multicore Hard Real-Time SystemsProceedings of the 28th International Conference on Real-Time Networks and Systems10.1145/3394810.3394825(11-21)Online publication date: 9-Jun-2020
    • (2019)Practical Progress Verification of Descriptor-Based Non-Blocking Data Structures2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2019.00019(83-93)Online publication date: Oct-2019

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