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View all- Brais HPanda P(2019)AlleriaACM Transactions on Embedded Computing Systems10.1145/335819318:5s(1-22)Online publication date: 8-Oct-2019
Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations
Article No.: 27, Pages 1 - 25
Abstract
Requiring no functional simulation, trace-driven simulation has the potential of achieving faster simulation speeds than execution-driven simulation of multicore architectures. An efficient, on-the-fly, high-fidelity trace generation method for multithreaded applications is reported. The generated trace is encoded in an instruction-like binary format that can be directly “interpreted” by a timing simulator to simulate a general load/store or x8-like architecture. A complete tool suite that has been developed and used for evaluation of the proposed method showed that it produces smaller traces over existing trace compression methods while retaining good fidelity including all threading- and synchronization-related events.
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- Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations
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Publication History
Published: 30 August 2017
Accepted: 01 May 2017
Revised: 01 March 2017
Received: 01 October 2016
Published in TACO Volume 14, Issue 3
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View all- Brais HPanda P(2019)AlleriaACM Transactions on Embedded Computing Systems10.1145/335819318:5s(1-22)Online publication date: 8-Oct-2019
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