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Timing-driven placement for FPGAs

Authors:

Alexander Marquardt,

Jonathan RoseAuthors Info & Claims

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Pages 203 - 213

https://doi.org/10.1145/329166.329208

Published: 01 February 2000 Publication History

Abstract

In this paper we introduce a new Simulated Annealing-based timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a novel method of determining source-sink connection delays during placement. Second, we introduce a new cost function that trades off between wire-use and critical path delay, resulting in significant reductions in critical path delay without significant increases in wire-use. Finally, we combine connection-based and path-based timing-analysis to obtain an algorithm that has the low time-complexity of connection-based timing-driven placement, while obtaining the quality of path-based timing-driven placement.

A comparison of our new algorithm to a well known non-timing-driven placement algorithm demonstrates that our algorithm is able to increase the post-place-and-route speed (using a full path-based timing-driven router and a realistic routing architecture) of 20 MCNC benchmark circuits by an average of 42%, while only increasing the minimum wiring requirements by an average of 5%.

References

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V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, February 1999.

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A. Marquardt, "Cluster-Based Architecture, Timing-Driven Packing. and Timing-Driven Placement for FPGAs," M.A.Sc. Thesis, University of Toronto, 1999.

Cited By

Nikolić SIenne P(2024)Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity PatternsACM Transactions on Reconfigurable Technology and Systems10.1145/359741717:1(1-39)Online publication date: 12-Feb-2024
https://dl.acm.org/doi/10.1145/3597417
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
Xiong ZRajarathnam RPan D(2024)A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00022(115-125)Online publication date: 5-May-2024
https://doi.org/10.1109/FCCM60383.2024.00022
Show More Cited By

Index Terms

Timing-driven placement for FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Conferences

FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

February 2000

223 pages

ISBN:1581131933

DOI:10.1145/329166

Chairmen:
Steve Trimberger
Xilinx, San Jose, CA
,
Scott Hauck
Univ. of Washington, Seattle

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 2000

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SIGDA

FPGA00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 10 - 11, 2000

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Nikolić SIenne P(2024)Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity PatternsACM Transactions on Reconfigurable Technology and Systems10.1145/359741717:1(1-39)Online publication date: 12-Feb-2024
https://dl.acm.org/doi/10.1145/3597417
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
Xiong ZRajarathnam RPan D(2024)A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00022(115-125)Online publication date: 5-May-2024
https://doi.org/10.1109/FCCM60383.2024.00022
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Yu LGuo B(2023)Timing-Driven Simulated Annealing for FPGA Placement in Neural Network RealizationElectronics10.3390/electronics1217356212:17(3562)Online publication date: 23-Aug-2023
https://doi.org/10.3390/electronics12173562
Taj IFarooq U(2023)Towards Machine Learning-Based FPGA Backend Flow: Challenges and OpportunitiesElectronics10.3390/electronics1204093512:4(935)Online publication date: 13-Feb-2023
https://doi.org/10.3390/electronics12040935
Yuan LYou HGuo G(2023)System Static Timing Analysis Method Based on Hierarchization2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218386(179-183)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218386
Shi KZhou XZhou HWang L(2022)An Optimized GIB Routing Architecture with Bent Wires for FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/351959916:1(1-28)Online publication date: 22-Dec-2022
https://dl.acm.org/doi/10.1145/3519599
Lin ZXie YZou PWang SYu JChen J(2022)An Incremental Placement Flow for Advanced FPGAs With Timing AwarenessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312007041:9(3092-3103)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120070
Elgammal MMurray KBetz V(2022)RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310986341:8(2532-2545)Online publication date: Aug-2022
https://doi.org/10.1109/TCAD.2021.3109863
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