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Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

Authors:

Honching Peter Li,

Toshiyuki Shibuya,

Dongmin XuAuthors Info & Claims

ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Pages 441 - 446

Published: 13 November 1997 Publication History

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Abstract

In this paper, we present an efficient Iterative Improvement based Partitioning (IIP) algorithm called LSR/MFFS, that combines signal flow based Maximum Fanout Free Subgraph (MFFS) clustering algorithm with Loose and Stable net Removal (LSR) partitioning algorithm. The MFFS algorithm generalizes existing MFFC decomposition method from combinational circuits to general sequential circuits in order to handle cycles naturally. We also study the properties of the nets that straddle the cutline carefully, and introduce the concepts of the loose and stable nets as well as effective ways to remove them out of the cutset. The LSR/MFFS algorithm first applies LSR algorithm to clustered netlist generated by MFFS algorithm for global-level cutsize optimization and then declusters netlist for further cutsize refinement. As a result, the LSR/MFFS algorithm has achieved the best cutsize result among all the bipartitioning algorithms published in the literatures with very promising runtime performance. In particular, it outperforms the recent state-of-the-art IIP algorithms LA3-CDIP, CLIP-PROPf, Strawman, hMetis-FM, and MLc by 17.4%, 12.1%, 5.9%, 3.1%, and 1.9%, respectively. It also outperforms the state-of-the-art non-IIP algorithms Paraboli, FBB, and PANZA by 32.0%, 21.4%, and 1.4%, respectively.

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Cited By

Zhu LChaudhuri ABanerjee SMurali GVanna-Iampikul PChakrabarty KLim S(2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
https://dl.acm.org/doi/10.1145/3473462
Park HKu BChang KShim DLim S(2021)Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and EnhancementsACM Transactions on Design Automation of Electronic Systems10.1145/345348026:5(1-25)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3453480
Hwang CPedram MTang T(2005)PMPProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120903(428-431)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120903
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Index Terms

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
1. Hardware
  1. Integrated circuits
    1. Logic circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors
2. Mathematics of computing
  1. Mathematical software

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Published In

cover image ACM Conferences

ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

November 1997

769 pages

ISBN:0818682000

Chairmen:
Ralph H. J. M. Otten
Delft Univ., delft, The Netherlands
,
Hiroto Yasuura
Kyushu Univ., Kasuga, Japan

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS: Computer Society

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IEEE Computer Society

United States

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Published: 13 November 1997

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Zhu LChaudhuri ABanerjee SMurali GVanna-Iampikul PChakrabarty KLim S(2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
https://dl.acm.org/doi/10.1145/3473462
Park HKu BChang KShim DLim S(2021)Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and EnhancementsACM Transactions on Design Automation of Electronic Systems10.1145/345348026:5(1-25)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3453480
Hwang CPedram MTang T(2005)PMPProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120903(428-431)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120903
Martinelli AKrenz RDubrova EImai M(2004)Disjoint-support Boolean decomposition combining functional and structural methodsProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015252(597-599)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015252
Selvakkumaran NRanjan ARaje SKarypis GMalik SFix LKahng A(2004)Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resourcesProceedings of the 41st annual Design Automation Conference10.1145/996566.996768(741-746)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996768
Saab Y(2004)An Effective Multilevel Algorithm for Bisecting Graphs and HypergraphsIEEE Transactions on Computers10.1109/TC.2004.353:6(641-652)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.3
Cherng JChen S(2003)An Efficient Multi-Level Partitioning Algorithm for VLSI CircuitsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835618Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835618
Cong JRomesis MXie MPedram MAlpert C(2003)Optimality, scalability and stability study of partitioning and placement algorithmsProceedings of the 2003 international symposium on Physical design10.1145/640000.640021(88-94)Online publication date: 6-Apr-2003
https://dl.acm.org/doi/10.1145/640000.640021
Li FHe LSaluja K(2002)Estimation of Maximum Power-up CurrentProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835440Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835440
Yan KGoto S(2001)Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocksProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370330(231-234)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370330
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