Browse Theses

A recurrent neural network with a recurrent learning rule is implemented using CMOS technology. We employ several building blocks for the implementation including a wide-range transconductance amplifier, a modified Gilbert multiplier, and a vector multiplier.

A sigmoid function generator is designed using the wide-range trans-conductance amplifier. The output of the wide-range transconductance amplifier is current. To convert the current output to voltage, we use active resistors. The modified Gilbert multiplier and the vector multiplier are implemented using current bus and active resistors. Their four-quadrant and dot-product multiplications are verified through the PSPICE circuit simulations.

We have developed a modified recurrent back-propagation learning rule for temporal learning. Its forward instantaneous update scheme is suitable for analog hardware implementations.

We have designed 4-neuron and 6-neuron recurrent neural network prototypes. We have implemented the neural network using standard CMOS circuits and verified their performance using extensive PSPICE circuit simulations. We have trained the two prototype neural networks to learn different state trajectories and the PSPICE circuit simulation shows that the recurrent neural network learn the temporal signals for reproduction and classification successfully.

Finally, a two-dimensional scalable array configuration is designed for a large-scale implementation of fully connected recurrent neural network with learning. With the 2-D array configuration, the layout offers a simple and scalable VLSI architecture.