research-article

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug

Authors:

Fatemeh Eslami,

Steven J.E. WiltonAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 44, Issue 4

Pages 20 - 25

https://doi.org/10.1145/3039902.3039907

Published: 11 January 2017 Publication History

Abstract

Embedded system designers can benefit from FPGA accelerators to achieve higher performance and efficiency. However, there are challenges that do not exist in software development; using software simulators to validate large and complex hardware designs can be extremely slow and impractical. Debugging designs implemented on an FPGA enables running the design at speed for long runs and more exhaustive test cases. However, limited observability is the primary challenge in hardware debug. To enhance hardware observability, trace-buffers and a trigger circuitry are inserted into the design. During the device operation, a history of signals of interest is recorded into the trace-buffers for off-line debug and validation. Recompiling the design every time the designer wishes to modify the trigger condition results in long debug turn-around times and reduced productivity. In this work, we present a pre-synthesized overlay fabric and algorithm to enable rapid triggering; during debug turn-around, TriggerPlus, a greedy algorithm, is used to implement a trigger circuit on the overlay. TriggerPlus is fast and simple, yet still capable of mapping the trigger circuit to the overlay fabric. We evaluate our techniques using VPR, showing that using our overlay and mapping algorithm together is at least an order of magnitude faster than the previous work resulting in a significant reduction in debug turn-around times.

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Cited By

Hale RHutchings B(2019)Preallocating Resources for Distributed Memory Based FPGA Debug2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00067(384-390)Online publication date: Sep-2019
https://doi.org/10.1109/FPL.2019.00067
Kourfali AFricke FHuebner MStroobandt D(2019)An Integrated on-Silicon Verification Method for FPGA OverlaysJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05786-z35:2(173-189)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10836-019-05786-z
Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Show More Cited By

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 44, Issue 4

HEART '16

September 2016

96 pages

ISSN:0163-5964

DOI:10.1145/3039902

Editor:
Babak Falsafi
Interim

Issue’s Table of Contents

Copyright © 2017 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 January 2017

Published in SIGARCH Volume 44, Issue 4

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Cited By

Hale RHutchings B(2019)Preallocating Resources for Distributed Memory Based FPGA Debug2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00067(384-390)Online publication date: Sep-2019
https://doi.org/10.1109/FPL.2019.00067
Kourfali AFricke FHuebner MStroobandt D(2019)An Integrated on-Silicon Verification Method for FPGA OverlaysJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05786-z35:2(173-189)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10836-019-05786-z
Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Eslami FHung EWilton S(2018)Extending post-silicon coverage measurement using time-multiplexed FPGA overlays2018 IEEE 23rd European Test Symposium (ETS)10.1109/ETS.2018.8400709(1-2)Online publication date: May-2018
https://doi.org/10.1109/ETS.2018.8400709

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