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ORCA a sea-of-gates place and route system

Authors:

M. Igusa,

M. Beardslee,

A. Sangiovanni-VicentelliAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 122 - 127

https://doi.org/10.1145/74382.74404

Published: 01 June 1989 Publication History

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Abstract

Sea-of-gates is becoming an important design style for Application Specific Integrated Circuits (ASICs). The sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. Very few systems are available today that can automatically layout sea-of-gates and none of these systems effectively use the features available in sea-of-gates architecture. ORCA is a place and route system for sea-of-gates, whose objective is to produce the highest density layout by fully exploiting the inherent features of this new design style. The ORCA system starts with a module generator which preprocesses memory arrays and other logic with a regular structure to form high density macros. The remaining logic is clustered together to form flexible macros, which we call porous. The porous macro-cells allow global routing to pass through the macro instead of detouring around its perimeter. The porous macros are dynamically shaped and resized by interaction with global wiring analysis. Finally, a general channelless area router has been developed to address the multiple layers of interconnect and routing areas which will be dominantly over-the-cell. Due to the large size of the problem (e.g. 100,000 gates), the placement and routing algorithms are hierarchical.

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Cited By

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Takahashi KNakajima KTerai MSato K(2006)Min-cut placement with global objective functions for large scale sea-of-gates arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.37236914:4(434-446)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.372369
Kao WParng T(2006)Cross point assignment with global rerouting for general-architecture designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.36512414:3(337-348)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.365124
Sutanthavibul SShragowitz ELin R(2006)An adaptive timing-driven placement for high performance VLSIsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25692212:10(1488-1498)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.256922
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Index Terms

ORCA a sea-of-gates place and route system
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Takahashi KNakajima KTerai MSato K(2006)Min-cut placement with global objective functions for large scale sea-of-gates arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.37236914:4(434-446)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.372369
Kao WParng T(2006)Cross point assignment with global rerouting for general-architecture designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.36512414:3(337-348)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.365124
Sutanthavibul SShragowitz ELin R(2006)An adaptive timing-driven placement for high performance VLSIsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25692212:10(1488-1498)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.256922
Setliff DRutenbar R(2006)On the feasibility of synthesizing CAD software from specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.13750710:6(783-801)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.137507
Koide TOno MWakabayashi SNishimaru Y(1997)Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIsProceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1997.600092(133-140)Online publication date: 1997
https://doi.org/10.1109/ASPDAC.1997.600092
Takahashi KNakajima KTerai MSato KJess JRudell R(1994)Adaptive cut line selection in min-cut placement for large scale sea-of-gates arraysProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191507(428-431)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191507
Terai MTakahashi KShirota HSato K(1994)A new efficient routing method for channel-less sea-of-gates arraysProceedings of IEEE Custom Integrated Circuits Conference - CICC '9410.1109/CICC.1994.379639(651-654)Online publication date: 1994
https://doi.org/10.1109/CICC.1994.379639
CHRZANOWSKA-JESKE MHER S(1994)I/O pad assignment for force-directed placement algorithmsInternational Journal of Electronics10.1080/0020721940892607977:4(467-479)Online publication date: Oct-1994
https://doi.org/10.1080/00207219408926079
Swartz WSechen CLightner MJess J(1993)A new generalized row-based global routerProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259875(491-498)Online publication date: 7-Nov-1993
https://dl.acm.org/doi/10.5555/259794.259875
Hoffmann A(1993)A new strategy for library-independent layout design1993 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1993.693084(2055-2058)Online publication date: 1993
https://doi.org/10.1109/ISCAS.1993.693084
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NTHU-route 2.0: a robust global router for modern designs

Fast place and route approaches for fpgas

NTHU-Route 2.0: a fast and stable global router

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NTHU-route 2.0: a robust global router for modern designs

Fast place and route approaches for fpgas

NTHU-Route 2.0: a fast and stable global router

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