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View all- Kologeski AZanuz HKastensmidt F(2016)Using traffic monitoring to tolerate multiple faults in 3D NoCs2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483341(63-68)Online publication date: Apr-2016
The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down ...
In this paper, we propose a method to design low latency and low energy networks for 3D Network-on-Chip (3D-NoC). Recent many-core processors require low-latency interconnection networks since the increasing number of cores limits the network ...
A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more ...
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