2009 Proceeding- General Chair:
- Paul Chow,
- Program Chair:
- Peter Cheung
FPGA 2009 is the 17th annual meeting of the ACM International Symposium on Field-Programmable Gate Arrays. As we gather again in Monterey, CA, we welcome you to this premier conference for the presentation of the latest research and advances in all areas related to FPGAs.
This year, we received 92 submissions from which we selected 24 excellent quality full papers for presentation at the Symposium (acceptance rate of 26%). This cohort of full-length papers provides a balanced program with strong contributions in the three areas of FPGA architecture (6), CAD tools (10) and applications (8).
In an effort to widen participation, we also introduce a new category known as "short papers", each having a 4-page publication, a short (5 minutes) presentation and a poster presentation. In all, eleven short papers were chosen. We will also have over 30 poster presentations that provide additional opportunities for researchers to present their work.
Delegates to this year's Symposium will enjoy an interesting pre-conference workshop on research challenges and opportunities in emerging applications, and an interesting debate during the Panel Session on Monday evening on "CMOS vs Nano: Comrades or Rivals?".
Proceeding Downloads
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap
Soft processors are often used in FPGA-based systems because of their ease-of-use, but for a given computation there is a significant gap in area/performance between a C code implementation executing on a soft processor and a custom FPGA hardware ...
Data streaming and simd support for the microblaze architecture
The MicroBlaze architecture is a configurable "soft core" processor by Xilinx intended for use in embedded FPGA applications. Some embedded data processing algorithms benefit from the use of vectorized code and streaming I/O. Thus, configurable ...
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation
Future generation multiprocessor system on chip (MPSOC) will be based on hundreds of processors connected through network on chips. One of the challenges is to tackle the design productivity required to reach this goal. We propose a NOC based small ...
Customizable bit-width in an OpenMP-based circuit design tool
As transistor density grows, increasingly complex hardware designs are implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of ...
Revisiting bitwidth optimizations
This paper revisits the classical bitwidth optimization problem for fixed-point designs. Our approach also starts from static analysis (range analysis and precision analysis) techniques. We first point out that AA-based precision analysis, which is ...
A clustering framework for task partitioning based on function-level data usage analysis
Recently, reconfigurable computing has received a great deal of attention due to its ability to increase an application performance with hardware execution, while possessing the flexibility of software solution. One of the major requirements for such ...
An intermediate hardware model with load/store unit for C to FPGA
We propose the semi-programmable hardware (SPHW) as an intermediate hardware that can be used by the designers and the high-level synthesis tools converting the C programs to FPGAs. The SPHW consists of a load/store unit (LSU), a reconfigurable register ...
N-port memory mapping for LUT-based FPGAs
As current FPGAs grow in logic capacity, they are widely used to implement entire systems. In some specific applications, such as our embedded multi-core processor TriBA[1],user memory models are not limited to single-port or dual-port. Thus, we need a ...
Parallel placement for FPGAs revisited
The runtime of classic sequential placement algorithms for FPGAs continues to represent a serious problem, aggravated by the continuous increase of FPGAs. The traditional way to parallelize the placement step is to use parallel distributed ...
Cited By
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Liu Y, Wang Z, Che B, Chen Y, Zhao J and Yue Y (2023). FPGA versus GPU for accelerating homomorphic encryption in federated learning International Workshop on Signal Processing and Machine Learning (WSPML 2023), 10.1117/12.3014890, 9781510671928, (55)
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Xue T, Wang Y, Deng X, Zhu S, Yu Q, Su J, Chen L and Chu J (2022). GPU implementation in real-time target search for push-broom hyperspectral imagery Eighth Symposium on Novel Photoelectronic Detection Technology and Applications, 10.1117/12.2619466, 9781510653115, (3)
Index Terms
- Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays