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- research-articleOctober 2019
3D NoCs with active interposer for multi-die systems
NOCS '19: Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-ChipArticle No.: 14, Pages 1–8https://doi.org/10.1145/3313231.3352380Advances in interconnect technologies for system-in-package manufacturing have re-introduced multi-chip module (MCM) architectures as an alternative to the current monolithic approach. MCMs or multi-die systems implement multiple smaller chiplets in a ...
- articleJune 2017
A low-overhead soft---hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems
The Journal of Supercomputing (JSCO), Volume 73, Issue 6Pages 2705–2729https://doi.org/10.1007/s11227-016-1951-0The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down ...
- research-articleAugust 2015
Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario
SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems DesignArticle No.: 29, Pages 1–6https://doi.org/10.1145/2800986.2801014The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). ...
- ArticleAugust 2014
Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method
HOTI '14: Proceedings of the 2014 IEEE 22nd Annual Symposium on High-Performance InterconnectsPages 63–70https://doi.org/10.1109/HOTI.2014.22The incorporation of the third dimension in the design of Networks-on-Chip (NoCs) provides a major performance improvement for Chip Multi-Processors (CMPs). Since multicast communication is necessary for parallelization, it is of significant importance ...
- research-articleMarch 2014
3D NoC with Inductive-Coupling Links for Building-Block SiPs
IEEE Transactions on Computers (ITCO), Volume 63, Issue 3Pages 748–763https://doi.org/10.1109/TC.2012.249A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more ...
- articleAugust 2013
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems (MSYS), Volume 37, Issue 6-7Pages 530–543https://doi.org/10.1016/j.micpro.2013.07.002Designing power-efficient Networks-on-Chips (NoCs) for 3D ICs has emerged as a promising solution for complex mobile and portable applications. The total power consumption of a 3D NoC design depends on the allocation of the Intellectual properties (IPs) ...
- ArticleMay 2008
The Shuffle-Exchange Mesh Topology for 3D NoCs
ISPAN '08: Proceedings of the The International Symposium on Parallel Architectures, Algorithms, and NetworksPages 275–280https://doi.org/10.1109/I-SPAN.2008.23Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of ...
- ArticleAugust 2007
Power consumption and performance analysis of 3D NoCs
ACSAC'07: Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems ArchitecturePages 209–219Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. Much research has been done in this field of study recently, e.g. in routing algorithms, switching methods, VLSI Layout, and effects of resource allocation on ...