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- research-articleJune 2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications
- Trong Huynh-Bao,
- Anabela Veloso,
- Sushil Sakhare,
- Philippe Matagne,
- Julien Ryckaert,
- Manu Perumkunnil,
- Davide Crotti,
- Farrukh Yasin,
- Alessio Spessot,
- Arnaud Furnemont,
- Gouri Kar,
- Anda Mocuta
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Article No.: 13, Pages 1–6https://doi.org/10.1145/3316781.3317886We present for the first time a co-integrated FinFET with vertical nanosheet transistor (VFET) process on a 300 mm silicon wafer for STT-MRAM applications and its related avenues with a holistic design-technology-co-optimization (DTCO) and power-...
