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- research-articleAugust 2014
ATCache: reducing DRAM cache latency via a small SRAM tag cache
PACT '14: Proceedings of the 23rd international conference on Parallel architectures and compilationPages 51–60https://doi.org/10.1145/2628071.26280893D-stacking technology has enabled the option of embedding a large DRAM onto the processor. Prior works have proposed to use this as a DRAM cache. Because of its large size (a DRAM cache can be in the order of hundreds of megabytes), the total size of ...
