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- abstractJune 2023
Architectural Support for Efficient Data Movement in Fully Disaggregated Systems
- Christina Giannoula,
- Kailong Huang,
- Jonathan Tang,
- Nectarios Koziris,
- Georgios Goumas,
- Zeshan Chishti,
- Nandita Vijaykumar
SIGMETRICS '23: Abstract Proceedings of the 2023 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer SystemsPages 5–6https://doi.org/10.1145/3578338.3593533Traditional data centers include monolithic servers that tightly integrate CPU, memory and disk (Figure 1a). Instead, Disaggregated Systems (DSs) [8, 13, 18, 27] organize multiple compute (CC), memory (MC) and storage devices as independent, failure-...
Also Published in:
ACM SIGMETRICS Performance Evaluation Review: Volume 51 Issue 1 - research-articleMarch 2023
DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems
- Christina Giannoula,
- Kailong Huang,
- Jonathan Tang,
- Nectarios Koziris,
- Georgios Goumas,
- Zeshan Chishti,
- Nandita Vijaykumar
Proceedings of the ACM on Measurement and Analysis of Computing Systems (POMACS), Volume 7, Issue 1Article No.: 16, Pages 1–36https://doi.org/10.1145/3579445Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory, and storage ...
- research-articleDecember 2019
Preventing zero-day exploits of memory vulnerabilities with guard lines
SSPREW9 '19: Proceedings of the 9th Workshop on Software Security, Protection, and Reverse EngineeringArticle No.: 2, Pages 1–11https://doi.org/10.1145/3371307.3371311Exploitable memory errors are pervasive due to the widespread use of unsafe programming languages, such as C and C++. Despite much research, techniques for detecting memory errors at runtime have seen limited adoption due to high performance overhead, ...
- research-articleJune 2018
Practical memory safety with REST
ISCA '18: Proceedings of the 45th Annual International Symposium on Computer ArchitecturePages 600–611https://doi.org/10.1109/ISCA.2018.00056In this paper, we propose Random Embedded Secret Tokens (REST), a simple hardware primitive to provide content-based checks, and show how it can be used to mitigate common types of spatial and temporal memory errors at very low cost. REST is simply a ...
- research-articleOctober 2017
PARSNIP: performant architecture for race safety with no impact on precision
MICRO-50 '17: Proceedings of the 50th Annual IEEE/ACM International Symposium on MicroarchitecturePages 490–502https://doi.org/10.1145/3123939.3123946Data race detection is a useful dynamic analysis for multithreaded programs that is a key building block in record-and-replay, enforcing strong consistency models, and detecting concurrency bugs. Existing software race detectors are precise but slow, ...
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- research-articleDecember 2015
Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study
ACM Transactions on Architecture and Code Optimization (TACO), Volume 12, Issue 4Article No.: 52, Pages 1–26https://doi.org/10.1145/2842686Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high ...
- ArticleMay 2015
Nexus#: A Distributed Hardware Task Manager for Task-Based Programming Models
IPDPS '15: Proceedings of the 2015 IEEE International Parallel and Distributed Processing SymposiumPages 1129–1138https://doi.org/10.1109/IPDPS.2015.79In the era of multicourse systems, it is expected that the number of cores that can be integrated on a single chip will be 3-digit. The key to utilize such a huge computational power is to extract the very fine parallelism in the user program. This is ...
- ArticleDecember 2013
Hardware-Supported Pointer Detection for Common Garbage Collections
CANDAR '13: Proceedings of the 2013 First International Symposium on Computing and NetworkingPages 134–140https://doi.org/10.1109/CANDAR.2013.26Many mobile systems have to achieve both high performance and low memory usage, and the total performance of the wide range of platforms now can be affected by the effectiveness of Garbage Collection (GC). GC algorithms have been actively studied and ...
- research-articleNovember 2013
ASIST: architectural support for instruction set randomization
CCS '13: Proceedings of the 2013 ACM SIGSAC conference on Computer & communications securityPages 981–992https://doi.org/10.1145/2508859.2516670Code injection attacks continue to pose a threat to today's computing systems, as they exploit software vulnerabilities to inject and execute arbitrary, malicious code. Instruction Set Randomization (ISR) is able to protect a system against remote ...
- ArticleAugust 2011
Nexus: Hardware Support for Task-Based Programming
DSD '11: Proceedings of the 2011 14th Euromicro Conference on Digital System DesignPages 442–445https://doi.org/10.1109/DSD.2011.62To improve the programmability of multicores, several task-based programming models have recently been proposed. Inter-task dependencies have to be resolved by either the programmer or a software runtime system, increasing the respectively. In this ...
- research-articleJuly 2011
Hardware-supported virtualization on ARM
APSys '11: Proceedings of the Second Asia-Pacific Workshop on SystemsArticle No.: 11, Pages 1–5https://doi.org/10.1145/2103799.2103813ARM is the dominant processor architecture for mobile devices and many other high-end embedded systems. Late last year ARM announced architectural support for virtualization, which will allow execution of unmodified guest operating system binaries. We ...
- research-articleSeptember 2010
Scalable hardware support for conditional parallelization
PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniquesPages 157–168https://doi.org/10.1145/1854273.1854297Parallel programming approaches based on task division/spawning are getting increasingly popular because they provide for a simple and elegant abstraction of parallelization, while achieving good performance on workloads which are traditionally complex ...
- ArticleSeptember 2010
A Case for Hardware Task Management Support for the StarSS Programming Model
DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and ToolsPages 347–354https://doi.org/10.1109/DSD.2010.63StarSS is a parallel programming model that eases the task of the programmer. He or she has to identify the tasks that can potentially be executed in parallel and the inputs and outputs of these tasks, while the runtime system takes care of the ...
- research-articleAugust 2009
NZTM: nonblocking zero-indirection transactional memory
SPAA '09: Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architecturesPages 204–213https://doi.org/10.1145/1583991.1584048This paper introduces NZTM, a nonblocking, zero-indirection, object-based, hybrid transactional memory system. NZTM comprises a nonblocking software transactional memory (STM) system that can exploit best-effort hardware transactional memory (HTM) if ...
- research-articleMay 2008
Execution suppression: An automated iterative technique for locating memory errors
ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 32, Issue 5Article No.: 17, Pages 1–36https://doi.org/10.1145/1745312.1745314By studying the behavior of several programs that crash due to memory errors, we observed that locating the errors can be challenging because significant propagation of corrupt memory values can occur prior to the point of the crash. In this article, we ...
- research-articleFebruary 2008
Hardware support for a wireless sensor network virtual machine
MOBILWARE '08: Proceedings of the 1st international conference on MOBILe Wireless MiddleWARE, Operating Systems, and ApplicationsArticle No.: 13, Pages 1–5Virtual Machines (VMs) have been proposed as an efficient programming model for Wireless Sensor Network (WSN) devices. However, the processing overhead required for VM execution has a significant impact on the power consumption and battery lifetime of ...
- research-articleNovember 2007
Effective memory protection using dynamic tainting
ASE '07: Proceedings of the 22nd IEEE/ACM International Conference on Automated Software EngineeringPages 284–292https://doi.org/10.1145/1321631.1321673Programs written in languages that provide direct access tomemory through pointers often contain memory-related faults, which may cause non-deterministic failures and even security vulnerabilities. In this paper, we present a new technique based on ...
- ArticleOctober 2007
Mark-sweep or copying?: a "best of both worlds" algorithm and a hardware-supported real-time implementation
ISMM '07: Proceedings of the 6th international symposium on Memory managementPages 173–182https://doi.org/10.1145/1296907.1296928Copying collectors offer a number of advantages over their mark-sweep counterparts. First, they do not have to deal with mark stacks and potential mark stack overflows. Second, they do not suffer from unpredictable fragmentation overheads since they ...
- research-articleJanuary 2007
AVIO: Detecting Atomicity Violations via Access-Interleaving Invariants
This article proposes an innovative concurrent-program invariant that captures programmers' atomicity assumptions. It describes a tool with two implementations, one in software and the other using hardware support, that can automatically extract such ...
- ArticleOctober 2006
Architectural support for software-based protection
ASID '06: Proceedings of the 1st workshop on Architectural and system support for improving software dependabilityPages 42–51https://doi.org/10.1145/1181309.1181316Control-Flow Integrity (CFI) is a property that guarantees program control flow cannot be subverted by a malicious adversary, even if the adversary has complete control of data memory. We have shown in prior work how CFI can be enforced by using inlined ...