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- research-articleFebruary 2024
Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis
ASPLOS '23: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4March 2023, Pages 87–107https://doi.org/10.1145/3623278.3624772Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive trials to obtain a ...
- research-articleNovember 2020
KFR: optimal cache management with <u>K</u>-<u>f</u>ramed <u>r</u>eclamation for drive-managed SMR disks
DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation ConferenceJuly 2020, Article No.: 241, Pages 1–6Shingled Magnetic Recording (SMR) disks have been proposed as a promising solution to satisfy the increasing capacity need in the big data era. Drive-Managed SMR (DM-SMR) disk which acts as a traditional block device is favored for providing high ...
- research-articleJune 2018
Improving runtime performance of deduplication system with host-managed SMR storage drives
DAC '18: Proceedings of the 55th Annual Design Automation ConferenceJune 2018, Article No.: 57, Pages 1–6https://doi.org/10.1145/3195970.3196063Due to the cost consideration for data storage, high-areal-density shingled-magnetic-recording (SMR) drives and data deduplication techniques are getting popular in many data storage services for the improvement of profit per storage unit. However, ...
- research-articleMay 2017
Task Transition Scheduling for Data-Adaptable Systems
- Nathan Sandoval,
- Casey Mackin,
- Sean Whitsitt,
- Vijay Shankar Gopinath,
- Sachidanand Mahadevan,
- Andrew Milakovich,
- Kyle Merry,
- Jonathan Sprinkle,
- Roman Lysecky
ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 4Article No.: 105, Pages 1–28https://doi.org/10.1145/3047498Data-adaptable embedded systems operate on a variety of data streams, which requires a large degree of configurability and adaptability to support runtime changes in data stream inputs. Data-adaptable reconfigurable embedded systems, when decomposed ...
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- research-articleSeptember 2013
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
- Andrew Canis,
- Jongsok Choi,
- Mark Aldham,
- Victor Zhang,
- Ahmed Kammoona,
- Tomasz Czajkowski,
- Stephen D. Brown,
- Jason H. Anderson
ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 2Article No.: 24, Pages 1–27https://doi.org/10.1145/2514740It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, ...
- ArticleApril 2013
System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems
ECBS '13: Proceedings of the 20th Annual IEEE International Conference and Workshops on the Engineering of Computer Based SystemsApril 2013, Pages 59–68https://doi.org/10.1109/ECBS.2013.25The complexity of embedded applications has led to highly configurable algorithms and standards that support a wide range of data inputs. Design time optimization of these algorithms is not possible due to combinatorial explosion of data configurations--...
- ArticleDecember 2012
Control-Flow Decoupling
MICRO-45: Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on MicroarchitectureDecember 2012, Pages 329–340https://doi.org/10.1109/MICRO.2012.38Mobile and PC/server class processor companies continue to roll out flagship core micro architectures that are faster than their predecessors. Meanwhile placing more cores on a chip coupled with constant supply voltage puts per-core energy consumption ...
- research-articleNovember 2012
Toward codesign in high performance computing systems
ICCAD '12: Proceedings of the International Conference on Computer-Aided DesignNovember 2012, Pages 443–449https://doi.org/10.1145/2429384.2429476Preparations for exascale computing have led to the realization that computing environments will be significantly different from those that provide petascale capabilities. This change is driven by energy constraints, which has compelled hardware ...
- ArticleJuly 2012
Viterbi Accelerator for Embedded Processor Datapaths
- Muhammad Waqar Azhar,
- Magnus Sjalander,
- Hasan Ali,
- Akshay Vijayashekar,
- Tung Thanh Hoang,
- Kashan Khurshid Ansari,
- Per Larsson-Edefors
ASAP '12: Proceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and ProcessorsJuly 2012, Pages 133–140https://doi.org/10.1109/ASAP.2012.24We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor datapath. We investigate the accelerator's impact on processor performance by using the EEMBC Viterbi benchmark and the in-...
- research-articleJune 2012
Dynamic Defragmentation of Reconfigurable Devices
- Sándor P. Fekete,
- Tom Kamphans,
- Nils Schweer,
- Christopher Tessars,
- Jan C. van der Veen,
- Josef Angermeier,
- Dirk Koch,
- Jürgen Teich
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 5, Issue 2Article No.: 8, Pages 1–20https://doi.org/10.1145/2209285.2209287We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based ...
- ArticleApril 2012
Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems
ECBS '12: Proceedings of the 2012 IEEE 19th International Conference and Workshops on Engineering of Computer-Based SystemsApril 2012, Pages 15–23https://doi.org/10.1109/ECBS.2012.16We present an overview of a data-adaptable reconfigurable embedded systems design methodology. The paper presents a novel paradigm for hardware/software code sign and reconfigurable computing driven by data-adaptability. The data-adaptable approach ...
- ArticleMarch 2012
Teaching hardware/software codesign on a reconfigurable computing platform
ARC'12: Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applicationsMarch 2012, Pages 264–275https://doi.org/10.1007/978-3-642-28365-9_22This paper reports on a practically oriented undergraduate course in Hardware/Software Codesign which uses an FPGA-based reconfigurable computing platform with a soft processor for analyzing and evaluating hardware/software trade-offs. The Altium ...
- research-articleMarch 2012
Automatic generation of hardware/software interfaces
ASPLOS XVII: Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating SystemsMarch 2012, Pages 325–336https://doi.org/10.1145/2150976.2151011Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the ...
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ACM SIGARCH Computer Architecture News: Volume 40 Issue 1, March 2012ACM SIGPLAN Notices: Volume 47 Issue 4, April 2012 - research-articleDecember 2011
Implementation and Evaluation of Raptor Codes on Embedded Systems
IEEE Transactions on Computers (ITCO), Volume 60, Issue 12December 2011, Pages 1678–1691https://doi.org/10.1109/TC.2010.210Raptor codes have been proven very suitable for mobile broadcast and multicast multimedia content delivery, and yet their computational complexity has not been investigated in the context of embedded systems. At the heart of Raptor codes are the matrix ...
- research-articleAugust 2011
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 3Article No.: 28, Pages 1–27https://doi.org/10.1145/2000832.2000840Current technology allows designers to implement complete embedded computing systems on a single FPGA. Using an FPGA as the implementation platform introduces greater flexibility into the design process and allows a new approach to embedded system ...
- ArticleApril 2011
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems
- Sachidanand Mahadevan,
- Vijay Shankar Gopinath,
- Roman Lysecky,
- Jonathan Sprinkle,
- Jerzy W. Rozenblit,
- Michael W. Marcellin
ECBS '11: Proceedings of the 2011 18th IEEE International Conference and Workshops on Engineering of Computer-Based SystemsApril 2011, Pages 34–43https://doi.org/10.1109/ECBS.2011.12Recent trends toward increased flexibility and configurability in emerging applications present demanding challenges for implementing systems that incorporate such capabilities. The resulting application configuration space is generally much larger than ...
- research-articleNovember 2010
Hardware/software codesign for a fuzzy autonomous road-following system
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews (TSMCPC), Volume 40, Issue 6November 2010, Pages 690–696https://doi.org/10.1109/TSMCC.2010.2049262In this research, a fuzzy logic controller is designed for vision-based autonomous road-following. Because of its high-speed response, portability, and flexibility, a field programmable gate array is applied to implement this control system. Furthermore,...
- abstractOctober 2010
Hardware/software co-design for high performance computing: challenges and opportunities
CODES/ISSS '10: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisOctober 2010, Pages 63–64https://doi.org/10.1145/1878961.1878975This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered ...
- research-articleMay 2010
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
IEEE Transactions on Computers (ITCO), Volume 59, Issue 5May 2010, Pages 651–665https://doi.org/10.1109/TC.2009.76As the semiconductor industry continues its relentless push for nano-CMOS technologies, device reliability and occurrence of hard errors have emerged as a dominant concern in multicores. Although regular memory structures are protected against hard ...