Export Citations
Save this search
Please login to be able to save your searches and receive alerts for new content matching your search criteria.
- research-articleNovember 1993
An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring
IEEE Transactions on Computers (ITCO), Volume 42, Issue 11Pages 1372–1381https://doi.org/10.1109/12.247847A new approach produces optimal signature placement for concurrent detection of processor and program-memory errors using signature monitoring. A program control-how graph, labeled with the overhead for placing a signature on each node and arc, is ...
- research-articleSeptember 1993
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers (ITCO), Volume 42, Issue 9Pages 1121–1131https://doi.org/10.1109/12.241600To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper, the authors consider the problem of optimally constructing the multiple scan chains to minimize the overall test time. Rather than ...
- research-articleAugust 1993
Test-Pattern Generation Based on Reed-Muller Coefficients
IEEE Transactions on Computers (ITCO), Volume 42, Issue 8Pages 968–980https://doi.org/10.1109/12.238487Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The ...
- research-articleAugust 1993
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers (ITCO), Volume 42, Issue 8Pages 898–912https://doi.org/10.1109/12.238481The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how,...
- research-articleJuly 1993
Design of Pseudoexhaustive Testable PLA with Low Overhead
IEEE Transactions on Computers (ITCO), Volume 42, Issue 7Pages 887–891https://doi.org/10.1109/12.237730The pseudoexhaustive testing (PET) scheme is an economical approach to testing a large embedded programmable logic array (PLA). The authors propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying this ...
-
- research-articleJune 1993
On Asymmetric Invalidation with Partial Tests
IEEE Transactions on Computers (ITCO), Volume 42, Issue 6Pages 764–768https://doi.org/10.1109/12.277298R. Gupta and I.V. Ramakrishnan (1987) proposed a general model for fault diagnosis that uniformly handles intermittent faults, masking, and partial testing. In this model, the diagnosability problem is open if asymmetric invalidation is used, although a ...
- research-articleMarch 1993
Vector Space Theoretic Analysis of Additive Cellular Automata and its Application for Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers (ITCO), Volume 42, Issue 3Pages 340–352https://doi.org/10.1109/12.210176A novel scheme for utilizing the regular structure of three neighborhood additive cellular automata (CAs) for pseudoexhaustive test pattern generation is introduced. The vector space generated by a CA can be decomposed into several cyclic subspaces. A ...
- research-articleMarch 1993
Expected-Value Analysis of Two Single Fault Diagnosis Algorithms
IEEE Transactions on Computers (ITCO), Volume 42, Issue 3Pages 272–280https://doi.org/10.1109/12.210170The problem of diagnosing single faults is addressed for systems whose fault propagation properties can be modeled as directed graphs. In these systems, the nodes represent components and the edges represent fault propagation between the components. ...
- research-articleMarch 1993
On the Equivalence of Fanout-Point Faults
IEEE Transactions on Computers (ITCO), Volume 42, Issue 3Pages 268–271https://doi.org/10.1109/12.210169Test-equivalent faults are commonly used in test generation and fault simulation to reduce the number of explicitly addressed faults. At the gate level, practical equivalence rules are confined to faults on the input and output terminals of Boolean ...
- research-articleFebruary 1993
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers
IEEE Transactions on Computers (ITCO), Volume 42, Issue 2Pages 179–189https://doi.org/10.1109/12.204791The problem of single stuck-at, stuck-open, and stuck-on fault detection in cascode voltage switch (CVS) parity trees is considered. The results are also applied to parity and two-rail checkers. It is shown that, if the parity tree consists of only ...
- research-articleFebruary 1993
A Characterization of Binary Decision Diagrams
IEEE Transactions on Computers (ITCO), Volume 42, Issue 2Pages 129–137https://doi.org/10.1109/12.204789Binary decision diagrams (BDDs) are a representation of Boolean functions. Its use in the synthesis, simulation, and testing of Boolean circuits has been proposed by various researchers. In all these applications of BDDs solutions to some fundamental ...
- research-articleJuly 1992
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay
IEEE Transactions on Computers (ITCO), Volume 41, Issue 7Pages 881–886https://doi.org/10.1109/12.256456An efficient technique for designing a totally self-checking checker for 1/n code (n<3) with minimum possible gate delay is proposed. The checker consists of a 1/n to k/2k translator and a k/2k code checker. The translator is implemented using a NOR ...
- research-articleJuly 1992
On the Testability of One-Dimensional ILAs for Multiple Sequential Faults
IEEE Transactions on Computers (ITCO), Volume 41, Issue 7Pages 906–916https://doi.org/10.1109/12.256448It is shown that one-dimensional, unilateral iterative logic arrays (ILAs) of combinational cells are C-testable for multiple sequential faults, provided the fault-free cell functions satisfy appropriate conditions. The test sequence is of length O((m/...
- research-articleJune 1992
The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers (ITCO), Volume 41, Issue 6Pages 688–698https://doi.org/10.1109/12.144621Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A ...
- research-articleMay 1992
A Testable Design of Logic Circuits Under Highly Observable Condition
IEEE Transactions on Computers (ITCO), Volume 41, Issue 5Pages 654–659https://doi.org/10.1109/12.142692The concept of k-UCP circuits is proposed. In a k-UCP circuit, all stuck-at faults and stuck-open faults can be detected and located by k+1 and k(k+1)+1 tests, respectively, under the highly observable condition. A method of modifying an arbitrary ...
- research-articleJanuary 1992
Statistical Resistance to Detection (Digital Circuits Testing)
IEEE Transactions on Computers (ITCO), Volume 41, Issue 1Pages 123–126https://doi.org/10.1109/12.123388Discusses the problem of estimating the sum of the detection probabilities of the yet unobserved faults during a random pattern test of a given digital circuit. The authors describe a statistical method for this purpose. The method requires keeping ...
- research-articleNovember 1991
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing-Module Insertion
IEEE Transactions on Computers (ITCO), Volume 40, Issue 11Pages 1198–1213https://doi.org/10.1109/12.102824The authors present a method for increasing the testability of combinational circuits for single stuck-at faults by partitioning the circuit and inserting testing-modules. A testing-module structure that allows lines in the circuit to be logically ...
- research-articleOctober 1991
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers (ITCO), Volume 40, Issue 10Pages 1133–1148https://doi.org/10.1109/12.93746The authors present a novel approach to the test generation problem for a more general class of two-dimensional iterative logic arrays (ILAs) than considered by previous researchers. For certain ILAs it is possible to find a test set whose size remains ...
- research-articleSeptember 1991
Analysis and Design of Linear Finite State Machines for Signature Analysis Testing
IEEE Transactions on Computers (ITCO), Volume 40, Issue 9Pages 1034–1045https://doi.org/10.1109/12.83659The authors present a theoretical investigation of the aliasing error probability (AEP) in signature analysis testing by means of linear finite state machines (LFSMs). The equations of the resulting Markov chain model of the LFSM are solved to determine ...
- research-articleSeptember 1991
Analysis of Detection Capability of Parallel Signature Analyzers
IEEE Transactions on Computers (ITCO), Volume 40, Issue 9Pages 1075–1081https://doi.org/10.1109/12.83655A rigorous mathematical analysis is presented to identify error conditions under which aliasing can occur for several common types of serial signature analyzers (SSAs) and parallel signature analyzers (PSAs). The PSAs are faster and require less ...
