The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it ...

The byte-addressable non-volatile memory (NVM) is a promising technology since it simultaneously provides DRAM-like performance, disk-like capacity, and persistency. The current NVM deployment with byte-addressability is \em symmetric, where NVM devices ...

Modern supercomputers have millions of cores, each capable of executing one or more threads of program execution. In these computers the site of execution for program threads rarely, if ever, changes from the node in which they were born. This paper ...

Derived by the demand for ever increasing computing performance, a steadily widening performance gap between memory and processor architectures has emerged. While attempting to mitigate the effects for processing systems that already face the exascale ...

We present an accurate online scalability prediction model for data-parallel programs on NUMA many-core systems. Memory contention is considered to be the major limiting factor of program scalability as data parallelism limits the amount of ...

Memory-CPU single communication channel bottleneck of the von Neumann architecture is quickly stalling the growth of computer processors. A probable solution to this problem is to fuse processing and memory elements. A simple low latency single on-chip ...

This Letter presents a novel purpose-designed architecture to realize efficient dual-port memory structures for image processing applications. The main innovation proposed here is the exploitation of single-port (SP) sub-banks to achieve the same data ...

Deployment of flash memory depends on making the most of its unique properties instead of treating it as a drop-in replacement for existing technologies.

In the context of portable embedded systems, reducing energy is one of the prime objectives. Memories are responsible for a significant percentage of a system’s aggregate energy consumption. Consequently, novel memories as well as novel memory ...

As processor speed continues, the gap between the processor cycle and the memory subsystem cycle is expected to grow. One solution to this growing problem is to maximize the first level (L1) cache hit ratio, therefore the mean memory access time can ...

In this paper, we present a new design-space exploration algorithm, the architecture explorer (AE), for analyzing performance/cost tradeoffs in memory-intensive applications. AE evaluates FU, bus, and memory cost for a series of performance constraints ...

A memory organized around a major/minor loop magnetic bubble storage unit contains database information in relational form. An external marker memory, consisting of an M-bit shift register or an M X 1 RAM, provides, in conjunction with an assumed ...