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- posterFebruary 2011
Symbolically modeling concurrent MCAPI executions
ACM SIGPLAN Notices (SIGPLAN), Volume 46, Issue 8August 2011, Pages 307–308https://doi.org/10.1145/2038037.1941602Improper use of Inter-Process Communication (IPC) within concurrent systems often creates data races which can lead to bugs that are challenging to discover. Techniques that use Satisfiability Modulo Theories (SMT) problems to symbolically model ...
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PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programming: ISBN 9781450301190, February 2011 - research-articleFebruary 2011
COREMU: a scalable and portable parallel full-system emulator
ACM SIGPLAN Notices (SIGPLAN), Volume 46, Issue 8August 2011, Pages 213–222https://doi.org/10.1145/2038037.1941583This paper presents the open-source COREMU, a scalable and portable parallel emulation framework that decouples the complexity of parallelizing full-system emulators from building a mature sequential one. The key observation is that CPU cores and ...
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PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programming: ISBN 9781450301190, February 2011 - keynoteFebruary 2011
How's the parallel computing revolution going?
ACM SIGPLAN Notices (SIGPLAN), Volume 46, Issue 8August 2011, Pages 123–124https://doi.org/10.1145/2038037.1941571Two trends changed the computing landscape over the past decade: (1) hardware vendors started delivering chip multiprocessors (CMPs) instead of uniprocessors, and (2) software developers increasingly chose managed languages instead of native languages. ...
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PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programming: ISBN 9781450301190, February 2011 - research-articleFebruary 2011
ULCC: a user-level facility for optimizing shared cache performance on multicores
ACM SIGPLAN Notices (SIGPLAN), Volume 46, Issue 8August 2011, Pages 103–112https://doi.org/10.1145/2038037.1941568Scientific applications face serious performance challenges on multicore processors, one of which is caused by access contention in last level shared caches from multiple running threads. The contention increases the number of long latency memory ...
Also Published in:
PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programming: ISBN 9781450301190, February 2011
