Multiply-and-accumulate (MAC) units are primarily utilized for convolution operations targeted towards signal and image processing workload. The compressors are applied at the partial product reduction stages to extract the multiplier output bits, which ...

Approximate arithmetic operators, such as adders and multipliers, are increasingly used to satisfy the energy and performance requirements of resource-constrained embedded systems. However, most of the available approximate operators have an application-...

Multiplication is a complex and substantial arithmetic task involved in signal processing applications. The hardware complexity of the multiplier is always high when compared with any other arithmetic operation. Approximate multiplication is a common ...

In combination with the Grenander--Szegö theorem, we observe that a relaxed positivity condition on multipliers, milder than the basic requirement of the Nevanlinna--Odeh multipliers that the sum of the absolute values of their components is strictly less ...

The main focus of the existing approximate arithmetic circuits has been on ASIC-based designs. However, due to the architectural differences between ASICs and FPGAs, comparable performance gains cannot be achieved for FPGA-based systems by using the ...

We present a simple approach to an analysis of higher order approximations to sets and functions. The objects we study are not of a specific order; they include objects of order 2 and $m$ with $m$ not necessarily an integer. We deduce from these concepts ...

Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energy-efficiency of a Bennett-clocked ...

This paper describes the micro-architectural and circuit design techniques for building complex VLSI circuits with micro-electromechanical (MEM) relays and presents experimental results to demonstrate the viability of this technology. By tailoring the ...

FPUs have been a topic of research for almost a century, leading to thousands of papers and books. Each advance focuses on the virtues of some specific new technique. This paper compares the energy efficiency of both throughput-optimized and latency-...

When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width ...

In this paper, we investigate the design and implementation of standard and fixed-width 8 x 8 multipliers using row bypassing technique. The design is described using VERILOG Hardware Descriptive Language and implemented using XILINX ISE 12.1v tool. ...

This paper presents the design and characterization of 12 full-adder circuits in the IBM 90-nm process. These include three new full-adder circuits using the recently proposed split-path data driven dynamic logic. Based on the logic function realized, ...

Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive ...

The paper proposes a class of switching modulators with reduced harmonics to allow a wide base band. In an ordinary switching modulator, the harmonics are rich and the operating bandwidth is rather limited. Here we are advancing a harmonic elimination ...

Contrary to the existing techniques to realize inexact circuits that relied mostly on scaling of supply voltage or pruning of "least-significant" components in conventional correct circuits to achieve cost (energy, delay and/or area) and accuracy ...

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to ...

This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. ...

Recently, passivity-based techniques to control the transmit power of mobile nodes have been proposed to ensure the finite gain stability of a class of cellular CDMA networks. These techniques implement the Zames-Falb multipliers at the mobile node and ...

This paper outlines a new sign extension technique for use in carry save adder trees that reduces the computational complexity. The "Negative Save" technique presented is a modification to the Baugh---Wooley sign extension technique developed for array ...