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- research-articleJuly 2024
P<sup>2</sup>-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1704–1717https://doi.org/10.1109/TVLSI.2024.3422684Vision transformers (ViTs) have excelled in computer vision (CV) tasks but are memory-consuming and computation-intensive, challenging their deployment on resource-constrained devices. To tackle this limitation, prior works have explored ViT-tailored ...
- research-articleOctober 2023
A Low-Noise Area-Efficient Column-Parallel ADC With an Input Triplet for a 120-dB High Dynamic Range CMOS Image Sensor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 31, Issue 12Pages 1939–1949https://doi.org/10.1109/TVLSI.2023.3323363This article presents and demonstrates the design of a high dynamic range (HDR) CMOS image sensor (CIS). Detailed operation of various comparator circuits is analyzed. A low-noise, area-efficient, wide-input range comparator is proposed for HDR ...
- research-articleOctober 2022
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 30, Issue 10Pages 1461–1472https://doi.org/10.1109/TVLSI.2022.3178615Multiobject detection has become an integral component in various neural applications, such as autonomous driving and augmented reality. The system should be able to recognize and process multiple objects simultaneously. Moreover, the performance ...
- research-articleJune 2022
A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic
- Kuo-Wei Chang,
- Hsu-Tung Shih,
- Tian-Sheuan Chang,
- Shang-Hong Tsai,
- Chih-Chyau Yang,
- Chien-Ming Wu,
- Chun-Ming Huang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 30, Issue 6Pages 816–825https://doi.org/10.1109/TVLSI.2022.3149768Memory bandwidth has become the real-time bottleneck of current deep learning accelerators (DLAs), particularly for high definition (HD) object detection. Under resource constraints, this article proposes a low memory traffic DLA chip with joint hardware ...
- research-articleNovember 2019
Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 27, Issue 11Pages 2693–2697https://doi.org/10.1109/TVLSI.2019.2932033Image dehazing is an essential preprocessing stage for several applications such as surveillance, long-range imaging, automatic driver-assistance system (ADAS), and remote sensing. Haze particles degrade visible-band images more severely than the infrared ...
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- research-articleOctober 2019
Model Order Reduction Method for Large-Scale <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> Interconnect and Implementation of Adaptive Digital PI Controller
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 27, Issue 10Pages 2447–2458https://doi.org/10.1109/TVLSI.2019.2922219Model order reduction is a powerful tool widely used in complexity reduction of high-dimensional systems. It is used to optimize the storage memory size and to design the adaptive control strategies of complex large-scale linear and nonlinear systems. In ...
- research-articleNovember 2018
Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 26, Issue 11Pages 2553–2566https://doi.org/10.1109/TVLSI.2018.2849438Owing to the limited response time of liquid crystal displays (LCDs), the motion-blurring effect is a critical problem to overcome for LCD applications. Among the available motion-blurring reduction methods, frame-rate upconversion (FRUC) presents an ...
- research-articleSeptember 2017
Energy-Efficient Object Detection Using Semantic Decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 9Pages 2673–2677https://doi.org/10.1109/TVLSI.2017.2707077In this brief, we present a new approach to optimize energy efficiency of object detection tasks using semantic decomposition to build a hierarchical classification framework. We observe that certain semantic information like color/texture is common ...
- research-articleMarch 2017
Hardware Implementation for Real-Time Haze Removal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 3Pages 1188–1192https://doi.org/10.1109/TVLSI.2016.2622404Haze removal is useful in computational photography and computer vision applications. Although many haze removal algorithms have been proposed, their computational efficiency requires improvement. A real-time haze removal method is presented in this ...
- research-articleMay 2016
A New Binary-Halved Clustering Method and ERT Processor for ASSR System
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 24, Issue 5Pages 1871–1884https://doi.org/10.1109/TVLSI.2015.2479259This paper presents an automatic speech–speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI design (here, ASSR system), the hardware cost and time complexity are ...
- research-articleApril 2016
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 24, Issue 4Pages 1305–1318https://doi.org/10.1109/TVLSI.2015.2462752Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the ...
- research-articleDecember 2015
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 23, Issue 12Pages 2913–2921https://doi.org/10.1109/TVLSI.2014.2382134Increasing demand of high-speed portable modules for multimedia applications has motivated the development of hardware-based solutions for image processing applications. Most of the nonrigid image registration algorithms are found to be unsuitable for ...
- research-articleOctober 2015
Memristive Threshold Logic Circuit Design of Fast Moving Object Detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 23, Issue 10Pages 2337–2341https://doi.org/10.1109/TVLSI.2014.2359801Real-time detection of moving objects involves memorization of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and component delays. ...
- research-articleOctober 2015
VLSI Design of a Depth Map Estimation Circuit Based on Structured Light Algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 23, Issue 10Pages 2281–2294https://doi.org/10.1109/TVLSI.2014.2357844In this paper, depth map estimation circuit design based on structured light is proposed, wherein a projection light source and an image sensor are utilized in combination to achieve a depth map estimation chip, an accurate, low complex circuit is ...
- research-articleOctober 2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 23, Issue 10Pages 2198–2208https://doi.org/10.1109/TVLSI.2014.2357181Video-based navigation (VBN) is increasingly used in space applications to enable autonomous entry, descent, and landing of aircrafts. VBN algorithms require real-time performances and high computational capabilities, especially to perform features ...
- research-articleMay 2013
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 21, Issue 5Pages 875–886https://doi.org/10.1109/TVLSI.2012.2202295In the piecewise function evaluation with polynomial approximation, nonuniform segmentation can effectively reduce the size of lookup tables for some arithmetic functions compared to uniform segmentation approaches, at the cost of the extra segment ...
- research-articleJanuary 2013
Algorithm and architecture design of bandwidth-oriented motion estimation for real-time mobile video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 21, Issue 1Pages 33–42https://doi.org/10.1109/TVLSI.2011.2178439This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data ...
- research-articleAugust 2012
Resource-efficient FPGA architecture and implementation of hough transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 20, Issue 8Pages 1419–1428https://doi.org/10.1109/TVLSI.2011.2160002Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of ...
- research-articleJune 2012
Parallel architecture for hierarchical optical flow estimation based on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 20, Issue 6Pages 1058–1067https://doi.org/10.1109/TVLSI.2011.2145423The proposed work presents a highly parallel architecture for motion estimation. Our system implements the well-known Lucas and Kanade algorithm with the multi-scale extension for the computation of large motion estimations in a dedicated device [field-...
- research-articleApril 2012
Design of an error detection and data recovery architecture for motion estimation testing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 20, Issue 4Pages 665–672https://doi.org/10.1109/TVLSI.2011.2109972Given the critical role of motion estimation (ME) in a video coder, testing such a module is of priority concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design, based ...