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- research-articleJune 2015
VIP: virtualizing IP chains on handheld platforms
- Nachiappan Chidambaram Nachiappan,
- Haibo Zhang,
- Jihyun Ryoo,
- Niranjan Soundararajan,
- Anand Sivasubramaniam,
- Mahmut T. Kandemir,
- Ravi Iyer,
- Chita R. Das
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 43, Issue 3SPages 655–667https://doi.org/10.1145/2872887.2750382Energy-efficient user-interactive and display-oriented applications on handhelds rely heavily on multiple accelerators (termed IP cores) to meet their periodic frame processing needs. Further, these platforms are starting to host multiple applications ...
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ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture: ISBN 9781450334020 - research-articleMarch 2015
DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 43, Issue 1Pages 207–221https://doi.org/10.1145/2786763.2694362Motivated by rapid software and hardware innovation in warehouse-scale computing (WSC), we visit the problem of warehouse-scale network design evaluation. A WSC is composed of about 30 arrays or clusters, each of which contains about 3000 servers, ...
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ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems: ISBN 9781450328357 - research-articleAugust 2011
Low power techniques for an android based phone
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 39, Issue 2Pages 26–35https://doi.org/10.1145/2024716.2024720Android is the latest trend in mobile operating systems. Even though Android provides a complete set of application, middleware and Linux kernel for the phone applications developer, it does not fully utilize several standard kernel features. This work ...
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- research-articleJune 2011
Prefetch-aware shared resource management for multi-core systems
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 39, Issue 3Pages 141–152https://doi.org/10.1145/2024723.2000081Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these shared resources; however, none of them take into account prefetch requests. ...
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ISCA '11: Proceedings of the 38th annual international symposium on Computer architecture: ISBN 9781450304726 - research-articleJune 2010
A case for FAME: FPGA architecture model execution
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 38, Issue 3Pages 290–301https://doi.org/10.1145/1816038.1815999Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Model Execution (FAME) simulators can increase the number of useful ...
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ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture: ISBN 9781450300537 - research-articleJune 2010
An integrated GPU power and performance model
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 38, Issue 3Pages 280–289https://doi.org/10.1145/1816038.1815998GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for programmers. Furthermore, optimizing for power consumption is ...
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ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture: ISBN 9781450300537 - research-articleMarch 2010
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 38, Issue 1Pages 335–346https://doi.org/10.1145/1735970.1736058Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed ...
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ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems: ISBN 9781605588391 - research-articleJune 2009
Flexible reference-counting-based hardware acceleration for garbage collection
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 37, Issue 3Pages 418–428https://doi.org/10.1145/1555815.1555806Languages featuring automatic memory management (garbage collection) are increasingly used to write all kinds of applications because they provide clear software engineering and security advantages. Unfortunately, garbage collection imposes a toll on ...
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ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture: ISBN 9781605585260 - research-articleJune 2009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 37, Issue 3Pages 152–163https://doi.org/10.1145/1555815.1555775GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance ...
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ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture: ISBN 9781605585260 - research-articleMarch 2008
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 36, Issue 1Pages 80–90https://doi.org/10.1145/1353534.1346293Indirect jump instructions are used to implement increasingly-common programming constructs such as virtual function calls, switch-case statements, jump tables, and interface calls. The performance impact of indirect jumps is likely to increase because ...
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ASPLOS XIII: Proceedings of the 13th international conference on Architectural support for programming languages and operating systems: ISBN 9781595939586 - articleJune 2007
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 35, Issue 2Pages 424–435https://doi.org/10.1145/1273440.1250715Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtual machine based runtime systems. Unfortunately, the prediction accuracy of indirect branches has not improved as much as that of ...
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ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture: ISBN 9781595937063 - articleDecember 2005
MonteSim: a Monte Carlo performance model for in-order microachitectures
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 33, Issue 5Pages 75–80https://doi.org/10.1145/1127577.1127592In this paper, we present a predictive Monte Carlo based performance model for in-order microarchitectures that is validated against the Itanium-2 processor. In such architectures, we find that application specific characteristics such as load carried ...
- articleDecember 2001
SIDE surfer: enriching casual meetings with spontaneous information gathering
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 29, Issue 5Pages 76–83https://doi.org/10.1145/563647.563661Development of wireless communications enables the rise of networking applications in mobile personal systems. Thus, Web access from wireless PDAs is now available. More recently, emergence of proximity and wireless communication technologies has ...
- articleSeptember 2000
LIDE: a simulation environment for shared virtual memory systems
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 28, Issue 4Pages 11–18https://doi.org/10.1145/362027.362029Shared Virtual Memory (SVM) systems are organizations of Distributed Shared Memory systems (DSM). These systems offer a shared memory programming model that is more intuitive than the message passing paradigm. Other advantages include low hardware and ...
- articleJune 2000
Exploiting parallelism in a network of workstations using COMA-BC
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 28, Issue 3Pages 1–8https://doi.org/10.1145/350755.350757In this paper we put forward a design for a multicomputer system based on a network of workstations which we call COMA-BC. It has a common address space in which a shared variables programming model can be used. The management of the shared address ...
- articleApril 1998
Design choices in the SHRIMP system: an empirical study
- Matthias A. Blumrich,
- Richard D. Alpert,
- Yuqun Chen,
- Douglas W. Clark,
- Stefanos N. Damianakis,
- Cezary Dubnicki,
- Edward W. Felten,
- Liviu Iftode,
- Kai Li,
- Margaret Martonosi,
- Robert A. Shillner
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 26, Issue 3Pages 330–341https://doi.org/10.1145/279361.279402The SHRIMP cluster-computing system has progressed to a point of relative maturity; a variety of applications are running on a 16-node system. We have enough experience to understand what we did right and wrong in designing and building the system. In ...
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ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture: ISBN 0818684917 - articleApril 1998
Active pages: a computation model for intelligent memory
ACM SIGARCH Computer Architecture News (SIGARCH), Volume 26, Issue 3Pages 192–203https://doi.org/10.1145/279361.279387Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive computations to the memory system. An Active Page consists of a page of data ...
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ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture: ISBN 0818684917