Burrows-Wheeler transform (BWT) has received special attention due to its effectiveness in lossless data compression algorithms. However, implementations of BWT-based algorithms have been limited due to the complexity of the suffix sorting process ...

In this paper, an FPGA arithmetic logic unit architecture for computing elliptic curve scalar multiplication over the binary extension field GF(2163) is presented. The proposed architecture implements a parallel version of the half-and-add method using ...

With the new and powerful Field Programmable Gate Array (FPGA) families, new possibilities have been opened. One of these features is the possibility of reconfiguring a section of the FPGA while the rest is working. Moreover, this fixed part could be ...

Development of PLDs (Programmable Logic Device) like large FPGA (Field Programmable Gate Array) circuits allow those to be used as modern control platforms for power electronics. Using FPGAs and efficient control algorithms better response times can be ...

General Purpose Processors (GPPs) and ASICs have traditionally been the common means for building and implementing Artificial Neural Networks (ANNs). However such computing paradigms suffer from the constant need of establishing a trade-off between ...

This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx® Spartan™-3 XC3S200 FPGA with the inclusion of a ...

The inherent parallelism of Artificial Neural Networks (ANNs) introduces several difficulties for its software implementation because of the sequential nature of von Neumann architectures. In contrast, hardware implementations offer the possibility to ...

One of the most extended algorithms for image scaling is bicubic interpolation. In this paper a Hardware Architecture for Bicubic Interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the ...

This article presents the design and implementation of a Self-Timed Arithmetic Logic Unit (ALU) that has been developed as part of an asynchronous microprocessor. This displays an inherent operational characteristic of low consumption, owing to the ...

We present Quartz, the first language supporting advanced features such as polymorphism, overloading, formal reasoning and generic VHDL library compilation, for correct and efficient reconfigurable design. Quartz is designed to support formal reasoning ...

The goals of this research are to examine the possibility of intrinsically evolving analogue neural networks on a Field Programmable Analogue Array (FPAA). This paper discusses initial progress in this area by detailing the hardware implementation of ...

When variables are assigned to registers or memories in FPGAs, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional units are writing to the same storage ...

In this paper we study a fundamental design problem for 2-level reconfigurable architectures (which are a special case of hyperreconfigurable architectures). On the lower reconfiguration level such architectures perform ordinary dynamic reconfiguration ...

Current and future communication schemes tend to use OFDM systems in order to provide high baud rates and less inter symbol interference. Some examples are 802.11, 802.16, MC-CDMA, Digital Video Broadcasting, Wireless USB and Wireless Firewire. Trying ...

This paper details the design and implementation of three uniform random number generators for use in massively parallel simulations in FPGAs. The three different generators are tailored to make use of three different types of hardware resource: logic, ...

We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power ...

Discrete wavelet transform is a powerful mathematical tool used for signal and image compression, nonlinear filtering or noise reduction, signal and biomedical image processing and all kind of applications that implies a time-located variation on ...

The present work focuses on the development of a reconfigurable systolic-based architecture for low-level image processing. The architecture is customizable providing the possibility to perform window operations for masks of 3 3, 5 5 and 7 7 ...

In this paper a novel field programmable gate array (FPGA) implementation of differential space vector pulse width modulator (DSVPWM) is presented. FPGA circuit was chosen because DSVPWM requires high computational power and its algorithms can be easily ...

Arithmetic operations over finite fields GF(2^m) are widely used in cryptography, error-correcting codes and signal processing. In particular, multiplication is especially relevant since other arithmetic operators, such as division or exponentiation, ...