Heterogeneous multicore processors promise high execution efficiency under diverse workloads, and program scheduling is critical in exploiting this efficiency. This paper presents a novel method to leverage the inherent characteristics of a program for ...

Today's computing environment is changing, with growing emphasis on reducing both operational energy costs and the high capital costs to reliably deliver power and cooling to systems in factory-sized data centers. The "greening" of data centers is ...

The environmental impact of data centers is significant and is growing rapidly. Servers alone in the US consumed 1.2% of the nation's energy in 2005, according to the EPA. In the following year, the EPA found that the cost of energy rose by 10%. However,...

Field-programmable gates arrays (FPGAs) are increasingly used in general-purpose computing platforms to augment microprocessors, enabling runtime loading of coprocessors customized to speed up some applications. Such transmuting coprocessors create new ...

Memory access latency and memory-related operations are often the performance bottleneck in parallel applications. In this paper, we present a concept of active memory operations which is an on-chip network transaction that operates based on the ...

Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-...

This paper suggests that the thermal state of a processor can be approximated using data flow analysis. The results of this analysis can be used to evaluate the efficacy of thermal-aware compilation strategies, or as input to thermal-aware optimizations ...

Consistent with the trend towards the use of many cores in SOC and 3D Chip techniques, this paper proposes a "single-cycle ring" interconnection (SC_Ring) with ultra-low latency and minimal complexity. The proposed SC_Ring allows multiple single-cycle ...

On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid ...

Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely -- from high-level descriptions down to gate-level ones -- to validate several aspects of the design, particularly functional ...

In this paper we will identify those aspects of the concurrent computing landscape that have changed since the 1980's and how those changes might impact the efficacy of parallel computing as we move from single- to multi- to many- and to massive numbers ...

Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques continuously monitor the on-chip processor temperature. Appropriate ...

This paper describes a rapid design methodology to create a pipeline of processers to execute streaming applications. The methodology is in two separate phases: the first phase, uses a heuristic to rapidly search through a large number of processor ...

Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. ...