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- ArticleFebruary 1998
Data cache sizing for embedded processor applications
We present a technique for determining the best data cache size required for a given memory-intensive application. A careful memory and cache line assignment strategy based on the analysis of the array access patterns effects a significant reduction in ...
- ArticleFebruary 1998
Embedded DRAM architectural trade-offs
In this paper we discuss system-related aspects in embedded DRAM/logic designs. We focus on large embedded memories which have to be implemented as DRAMs.
- ArticleFebruary 1998
An energy-conscious exploration methodology for reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a variety of the macromodules (micro-processors, DSPs, programmable logic and embedded ...
- ArticleFebruary 1998
Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays
Although several methods for array design validation have been proposed and had great success in the past, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we propose ...
- ArticleFebruary 1998
Efficient compilation of process-based concurrent programs without run-time scheduling
Currently, run-time operating systems are widely used to implement concurrent embedded applications. This run-time approach to multi-tasking and inter-process communication can introduce significant overhead to execution times and memory requirements -- ...
- ArticleFebruary 1998
Smart pixel implementation of a 2-D parallel nucleic wavelet transform for mobile multimedia communications
A novel Smart Pixel Opto-VLSI architecture to implement a complete 2-D wavelet transform of real-time captured images is presented. The Smart Pixel architecture enables the realization of a highly parallel, compact, low power device capable of real-time ...
- ArticleFebruary 1998
Scheduling of conditional process graphs for the synthesis of embedded systems
We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which ...
- ArticleFebruary 1998
Stream communication between real-time tasks in a high-performance multiprocessor
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing architectures can deliver. The Prophid heterogeneous multiprocessor architecture ...
- ArticleFebruary 1998
CASPER: concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures
Hardware-software co-synthesis of an embedded system requires mapping of its specifications into hardware and software modules such that its real-time and other constraints are met. Embedded system specifications are generally represented by acyclic ...