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- research-articleDecember 2015
Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study
ACM Transactions on Architecture and Code Optimization (TACO), Volume 12, Issue 4Article No.: 52, Pages 1–26https://doi.org/10.1145/2842686Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high ...
- research-articleDecember 2014
Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks
ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 4Article No.: 43, Pages 1–19https://doi.org/10.1145/2677160Compared with either block or page-mapping Flash Translation Layer (FTL), hybrid-mapping FTL for flash Solid State Disks (SSDs), such as Fully Associative Section Translation (FAST), has relatively high space efficiency because of its smaller mapping ...
- research-articleSeptember 2013
An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA
ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, Issue 3Article No.: 15, Pages 1–25https://doi.org/10.1145/2509420.2509426In application-specific processor design, a common approach to improve performance and efficiency is to use special instructions that execute complex operation patterns. However, in a generic embedded processor with compact Instruction Set Architecture (...
