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- research-articleFebruary 2024
Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis
ASPLOS '23: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4March 2023, Pages 87–107https://doi.org/10.1145/3623278.3624772Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive trials to obtain a ...
- research-articleFebruary 2024
MiniMalloc: A Lightweight Memory Allocator for Hardware-Accelerated Machine Learning
ASPLOS '23: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4March 2023, Pages 238–252https://doi.org/10.1145/3623278.3624752We present a new approach to static memory allocation, a key problem that arises in the compilation of machine learning models onto the resources of a specialized hardware accelerator. Our methodology involves a recursive depth-first search that limits ...
- research-articleFebruary 2024
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
ASPLOS '23: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4March 2023, Pages 219–237https://doi.org/10.1145/3623278.3624750The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. ...